We are designing a microTCA module called the DTC (DAQ and Timing Card) for the HCAL SLHC readout. It is currently envisioned that this will occupy one of the MCH slots in a dual-star type crate. Initially we would build cards for MCH connectors 1 and 2, providing clock distribution on finger 2, and fast controls and trigger feedback on port 1 of fabric A on finger 1.

• DTC_SPecification.pdf – preliminary description – updated 5/17.09
• PICMG standards – EDF only: username / password required
• Documentation for CorEdge mini uTCA systems we have 2 of
  • System • Power Module
• SuperHTR Documentation (aka "miniCTR2" or "SHTR")
• Vadatech VT891 μTCA crate specs – Original or Local copy

Design Thoughts

Clocking – per AMC spec:

Type	AMC Name	μTCA Name	Contacts	Direction
Telecom	TCLKA	CLK1	74/75	In to AMC
Telecom	TCLKC	CLK3	135/136	In to AMC
Fabric	FCLKA		80/81	In to AMC
Telecom	TCLKB	CLK2	77/78	Out from AMC
Telecom	TCLKD		138/139	Out from AMC

On the CTR2 FCLKA, TCLKA and TCLKC all enter an SN65LVDT125A LVDS crosspoint switch, and from there can be routed to the FPGA or links, possibly via an Si5319 frequency synthesizer.

It is challenging to understand the AMC and µTCA clocking. My current understanding is that dual-star backplanes typically fanout one clock from each MCH to each AMC, and return one clock from each AMC to either MCH. This implies to me that we should use the single clock as a fixed-frequency link clock and that the LHC clock should be embedded in the stream sent on fabric port 1 from the MCH to the AMCs.

Parts

• Harting MCH connectors
• HFBR-2316T – TTC fiber receiver photo-diode
• Molex 74754-0101 – SFP+ optical transceiver cage

-- EricHazen - 03 Oct 2009