This page contains some
uHTRTool
software procedures which are useful to an AMC13 debugger and developer.
Program uHTR Flash
The uHTR consists of two FPGAs, a 'front' and a 'back'. You can find the firmware files for each chip
here
- Make sure that the firmware files you want to program into the module are located in the current directory.
- Start
uHTRtool.exe
, giving it the IP address of the uHTR you want to reprogram. NOTE! If using IPbus Software Suite 2.0 or greater, you need to use teh -u
option for the time being, as ControlHub
is not yet working
uHTRtool.exe -u 192.168.115.8
(0) IP[192.168.115.8] Type: UHTR
ID of uHTR (-1 for exiting the tool) ::
Front Firmware revision : (00) 00.07.00
Back Firmware revision : (00) 00.08.00
- Go to the
FLASH
section and select PROG
> flash
FLASH target: BACK
FPGA Toggle which FPGA to target
READ Read the flash contents into a file
PROG Reprogram the flash from an MCS file
VERIFY Verify the flash contents against an existing MCS file
RELOAD Reload the FPGA from FLASH
QUIT Back to top menu
>
- Toggle to the FPGA you want to program by using the
FPGA
command. Notice that BACK
is the default
- Select the
PROG
option from the menu
FLASH target: BACK
FPGA Toggle which FPGA to target
READ Read the flash contents into a file
PROG Reprogram the flash from an MCS file
VERIFY Verify the flash contents against an existing MCS file
RELOAD Reload the FPGA from FLASH
QUIT Back to top menu
> prog
- Enter the path of the MCS file you want to program into the FPGA. If you followed step 1, this should just be the file name, since it sits in the current directory. MAKE SURE YOU PROGRAM THE CORRECT MCS FILE INTO THE CHOSEN FPGA! DON'T GO PUTTING A 'FRONT' FIRMWARE FILE INTO THE 'BACK' FPGA OR VICE VERSA!
MCS file: uhtr_back_0_8_30.mcs.xz
Unpacking XZ uhtr_back_0_8_30.mcs.xz into /tmp/uHTR_chill90.mcs
Line count: 333294
Sector-by-sector programming (21 sectors)
Sector 00 : erasing... writing data... verifying... (ok)
Sector 01 : erasing... writing data... verifying... (ok)
[...]
- If no errors are reported, then you are ready to reload the FPGA from flash using the
RELOAD
command
FLASH target: BACK
FPGA Toggle which FPGA to target
READ Read the flash contents into a file
PROG Reprogram the flash from an MCS file
VERIFY Verify the flash contents against an existing MCS file
RELOAD Reload the FPGA from FLASH
QUIT Back to top menu
> reload
Initiating reload from flash (requires ~10 seconds)...
- Now go back to the main menu, check the status, and see that your firmware version has been successfully updated
> quit
[...]
> status
Front Firmware revision : (00) 00.07.00
Back Firmware revision : (00) 00.08.30
- Congratulations! The
BACK
FPGA on your uHTR has been updated! The process for the FRONT
FPGA is identical, only that you need to toggle to the FRONT
and program the chip with a front
MCS file.
Enable uHTR DAQ Path
- Start
uHTRtool.exe
, giving it the IP address of the uHTR you want to reprogram. NOTE! If using IPbus Software Suite 2.0 or greater, you need to use teh -u
option for the time being, as ControlHub
is not yet working
uHTRtool.exe -u 192.168.115.8
(0) IP[192.168.115.8] Type: UHTR
ID of uHTR (-1 for exiting the tool) ::
Front Firmware revision : (00) 00.07.00
Back Firmware revision : (00) 00.08.00
- Enter the
DAQ
command to go the DAQ menu
> daq
STATUS Status of the DAQ path
SPY Read the DAQ path spy
CTL Control the DAQ path
F2B F2B DAQ Link Operations
QUIT Back to top menu
- Check the DAQ menu
STATUS
to make to see if your DAQ Path is already enabled
> status
DAQ F2B Links
0 : Status = f Errors = 11950 (0.000000e+00 Hz) Words = 6022 (0.000000e+00 Hz)
1 : Status = f Errors = 12042 (0.000000e+00 Hz) Words = 6068 (0.000000e+00 Hz)
2 : Status = f Errors = 11950 (0.000000e+00 Hz) Words = 6022 (0.000000e+00 Hz)
DAQ Path : DISABLED ZS(per sample)
Last EVN: 0 OrN : 0 Header Occupancy : 0 (Peak : 0)
Samples: 0 Presamples : 0 Pipeline Length : 0
ZS Mask (one means ignore) : 0x 0
TP Samples: 0 TP Presamples : 0
TP ZS : TP_NZS
Module Id : 0 (0x0) BC Offset : 0
- (If you want to reset the link, first disable it if not already enable)
- If it is not enabled, enable it with the following configuration (as provided by Shih-Chuan)
> ctl
[...]
(1) Set Module Id (2) Set BC Offset (3) Set NSAMPLES
(4) Set PRESAMPLES (5) Set Pipeline Length (6) Set ZS Mask
(7) Enable DAQ Path (toggle) (8) Reset DAQ Path
(9) Toggle NZS (10) Toggle Mark-And-Pass ZS (11) Toggle ZS Sum-By-Two
(12) Dump ZS Thresholds (13) Edit ZS Thresholds (14) Uniform ZS
(15) Set TP PRESAMPLES (16) Set TP SAMPLES
(17) Toggle ZS for TP (18) Toggle SOI-only for TP
( Anything else will just return to the original menu )
Selection : [-1] 3
New nsamples : [0] 10
[...]
Selection : [-1] 4
New presamples : [0] 4
[...]
Selection : [-1] 5
New pipeline length : [0] 8
[...]
Selection : [-1] 15
TP presamples : [2] 2
Selection : [-1] 16
TP samples : [2] 2
Selection : [-1] 7
[...]
Selection : [-1] 8
- Now go back to the DAQ menu, check the status, and you should see that your DAQ path is ready to go!
Selection : [-1] -1
[...]
> status
DAQ F2B Links
0 : Status = f Errors = 11950 (0.000000e+00 Hz) Words = 6022 (0.000000e+00 Hz)
1 : Status = f Errors = 12042 (0.000000e+00 Hz) Words = 6068 (0.000000e+00 Hz)
2 : Status = f Errors = 11950 (0.000000e+00 Hz) Words = 6022 (0.000000e+00 Hz)
DAQ Path : ENABLED ZS(per sample)
Last EVN: 0 OrN : 0 Header Occupancy : 0 (Peak : 0)
Samples: 10 Presamples : 4 Pipeline Length : 50
ZS Mask (one means ignore) : 0x 0
TP Samples: 0 TP Presamples : 0
TP ZS : TP_NZS
Module Id : 0 (0x0) BC Offset : 0
Old DAQ enabled menu options:
Selection : [-1] 3
New nsamples : [0] 10
[...]
Selection : [-1] 4
New presamples : [0] 4
[...]
Selection : [-1] 5
New pipeline length : [0] 50
[...]
Selection : [-1] 7
[...]
Selection : [-1] 8
- Now go back to the DAQ menu, check the status, and you should see that your DAQ path is ready to go!
Setup Clock
When checking the status of you uHTR, a list of the clocks are reported (for both front and back). These reported clocks should be consistent with the expected clock (see below). Inconsistencies may indicate that you will need to setup clocks.
ID[0] IP[192.168.115.8] Type: uHTR
ID of uHTR (-1 for exiting the tool) :: [0]
Front Firmware revision : (00) 00.09.00
Back Firmware revision : (00) 00.0b.00
Clock expected at 25.0000 MHz : 25.0000 MHz (front) 25.0000 MHz (back)
Clock expected at 100.0000 MHz : 100.0000 MHz (front) 100.0000 MHz (back)
Clock expected at 40.0800 MHz : 40.0796 MHz (front) 40.0795 MHz (back)
Clock expected at 80.1600 MHz : 80.1591 MHz (front) 80.1591 MHz (back)
Clock expected at 120.2400 MHz : 120.2387 MHz (front) 120.2387 MHz (back)
Clock expected at 160.3200 MHz : 160.3183 MHz (front) 160.3183 MHz (back)
Clock expected at 240.4800 MHz : 240.4774 MHz (front) 240.4775 MHz (back)
Clock expected at 320.6400 MHz : 320.6366 MHz (front) 320.6366 MHz (back)
Clock expected at 11.0000 kHz : 11.2450 kHz (front) 11.2460 kHz (back)
Clock expected at 0.1100 kHz : 0.0000 kHz (front) 0.0000 kHz (back)
Clock expected at 40.0800 MHz : 40.0796 MHz (front) 40.0795 MHz (back)
Clock expected at 40.0800 MHz : 40.0796 MHz (front) 40.0795 MHz (back)
Clock expected at 240.4800 MHz : 240.4775 MHz (front) 320.6366 MHz (back)
The following is the procedure to setup clocks
CLOCK
SETUP
Standard 1.6 Gbps setup (1), Standard 4.8 Gbps setup (2) or custom (3)? [1] 1
LUMI
RESET
Send uHTR Local Triggers
The following procedure assumes that the backplane link sees Bc0s running both ways between the uHTR and the AMC13. It's also worth saying that the following procedure is from Jeremy, and that upon it's initial test, it did not work. We are not sure what the problem is yet, but this list of command may need to be modified.
LINK
FE_RAMS
SETUP
Enable? = 1
TTC aligned? = 1
Delay between TTC oribt and pattern start = 0
ISOPULSE
Fiber = 6
Chan = 2
Amplitude = 20
Bunch = 300
TRIG
LUTS
Set 1-1 LUT
Which group of LUTs? = 0
Choose index = -1
Set 1-1 LUT
Which group of LUTs? = 1
Choose index = -1
TRIG
SELF
Set thresholds
Which threshold = -1
Set to what value? = 5
--
CharlieHill - 31 May 2013