Testing HTR histogramming firmware 0x14200. Program into HTR in slot 18, which is connected to a DCC2 in slot 11 spigots 10, 11. Use manual triggers for now. Send 10 L1A by writing to VME register on TTCvi.

Data does not look good. DCC reports HTR CRC errors on every event, and various LRB errors.

• histo1.txt – hex dump
• histo1.dat – raw binary data

Now try with DCC1:

$ DCCdiagnose.exe
> dcc/init 0 1       # initialize two spigots
> dcc/stop           # make sure DCC is not in run mode to stop event building
> ttc/l1a            # make an L1A
> lrb/stat 1         # check LRB status
mip1_conf [40] 003e0263 [44] 00003601
Chan Empty Full Blocks Header CERR UERR IDER -WORD- -NBLK-
 0     Yes   No     No     No 0000 0000 0000 000000 000000
 1      No   No    Yes    Yes 000e 0002 0000 00018a 000001
 2      No   No    Yes    Yes 0009 0006 0000 00018a 000001
> 
>lrb/read 1 2
DEBUG: LRB config was 0x003e0263
DEBUG: LRB config now 0x003e0263
Set LRB to single-word PCI transfer mode
Reading one block (event fragment)
FIFO empty (status=b0001205) after 788 words
Saw Trailer
0x0314 16-bit words read
0000: 0202 H
0001: 0000 D
0002: a040 D
0003: 00cb D
0004: 065f D
0005: 5403 D
0006: a006 D
0007: 00ff D
0008: 0000 D
0009: 0000 D
 ...
030b: 0000 D
030c: 0000 D
030d: 0000 D
030e: 0000 D
030f: 0000 D
0310: 0000 D
0311: 0312 D
0312: 018a D
0313: 02c3 T
>

There is trouble right away. In the LRB status word at the end, we see status code 0xc3 (refer to LRB documentation) we see that the following bits are set:

• ODD – odd number of 16-bit words seen
• STRUC – Header/Data/Trailer order not respected (not certain what this means exactly in the world where we only send one S bit)
• UERR, CERR – both corrected and uncorrected hamming errors

Power cycle the crate, now the HTR in slot 18 will not send any data. Doubtless there is some incompatibility in the registers between the histogramming firmware and the real firmware. . Going to lunch.

Another try. Send one event, look at LRB regs:

>lrb/stat 1
mip1_conf [40] 003e0263 [44] 00003601
Chan Empty Full Blocks Header CERR UERR IDER -WORD- -NBLK-
 0     Yes   No     No     No 0000 0000 0000 000000 000000
 1      No   No    Yes    Yes 000f 0003 0000 00018a 000001
 2      No   No    Yes    Yes 000b 0001 0000 00018a 000001
>ttc/l1a
1 L1A generated
>lrb/stat 1
mip1_conf [40] 003e0263 [44] 00003601
Chan Empty Full Blocks Header CERR UERR IDER -WORD- -NBLK-
 0     Yes   No     No     No 0000 0000 0000 000000 000000
 1      No   No    Yes    Yes 001e 0005 0000 000314 000002
 2      No   No    Yes    Yes 0018 0002 0000 000314 000002
>ttc/l1a
1 L1A generated
>lrb/stat 1
mip1_conf [40] 003e0263 [44] 00003601
Chan Empty Full Blocks Header CERR UERR IDER -WORD- -NBLK-
 0     Yes   No     No     No 0000 0000 0000 000000 000000
 1      No   No    Yes    Yes 002b 000a 0001 00049f 000003
 2      No   No    Yes    Yes 0023 0003 0000 00049e 000003
>ttc/l1a
1 L1A generated
>lrb/stat 1
mip1_conf [40] 003e0263 [44] 00003601
Chan Empty Full Blocks Header CERR UERR IDER -WORD- -NBLK-
 0     Yes   No     No     No 0000 0000 0000 000000 000000
 1      No   No    Yes    Yes 003c 000b 0001 000629 000004
 2      No   No    Yes    Yes 002c 0006 0000 000628 000004
>

The number of UERR and CERR varies widely from blcck to block. The number of words is sometimes off by one (one extra 16-bit word).

-- EricHazen - 10 Apr 2009