HTR to DCC2 links use National DS90CR285/286 Channel Link technology. These are in principle 28 bit links but we only use 24 of them. The low-level link format is as shown in the table below from 2008 onwards.

HTR Input	Function	Notes
0	H0	Hamming code bit 0
1	H1	Hamming code bit 1
2	D0	Data bit 0
3	H2	Hamming code bit 2
4	D1	Data bit 1
5	x	Not used due to PCB layout crosstalk issue (ignored by DCC)
6	D3	Data bit 3
7	H3	Hamming code bit 3
8	D4	Data bit 4
9	D5	Data bit 5
10	D6	Data bit 6
11	D7	Data bit 7
12	D8	Data bit 8
13	S1	Framing bit, set to '1' for header and trailer words only
14	D10	Data bit 10
15	H4	Hamming code bit 4
16	D11	Data bit 11
17	D12	Data bit 12
18	D13	Data bit 13
19	D14	Data bit 14
20	D15	Data bit 15
21	D2	Data bit 2
22	D9	Data bit 9
23	P	Parity bit

Bits 0-23 only are connected on the DS90CR285 transmitter on the HTR (See HTR Schematic excerpt).

Of the 24 bits, 16 are used for data. Of the remaining 8, originally two were used for framing bits (named S0, S1) and the other 6 were for ECC coding. The original format is described here. This was changed due to the PCB layout problem described here in ~2008.

In the DCC2, a Channel Link receiver is not used but instead a deserializer implemented in a Spartan-3 FPGA.

-- EricHazen - 09 Oct 2012