10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.

Boards are numbered in decimal starting with 2001 for the first prototype up to a maximum possible number of 2255. The first digit is always '2'. The other three digits represent the decimal equivalent of the binary value set by cutting jumpers on the PCB.

You can find out which board is where in the pit as follows:

(log on to a head node, i.e. cmsusr1 etc)

$ cd ~ehazen/GetStatus
$ ./getAllVersions.sh | ./parseVersions.pl

 Crate  Bus    Slot   Xilinx     LRB        VME    S/N  FED
 ====================================
     4  caen:0 10     0x3018     0x010a     0x0104 2001 700
     4  caen:0 20     0x3018     0x010a     0x0104 2002 701
     0  caen:1 10     0x3018     0x010a     0x0104 2174 702
     0  caen:1 20     0x3018     0x010a     0x0104 2176 703
       .... remainder of list truncated ...

Here is Dick Kellogg's list which may become the official one. For now, you have to check both.

Prototype Boards

S/N	Location	Notes
2001	FED_701	Tested in MWGR 15
2002	904
2003	904
2004	904
2005	BU - Test stand
2006	Whitman	To be destructively tested for soldering temperature profiles
2007	BU	Ethernet resistor replaced - re-test
2008	BU	Ethernet resistor replaced - re-test
2009	BU	Tested. No errors
2010	BU

Production Boards

The production board serial numbers start with 2129 as shown below. On the PCB, the binary "jumpers" (actually cut traces) start with "10000001".

Note that you can sort the table below by clicking the column headings. Sort by Location for an easy way to check how many boards are where.

S/N	Location	Notes	Last update	Status
2129	FED_730	Tested.	5/26	OK
2130	FED_727	1 July 2009: Orbit number mismatches as FED 731 (removed) 31 July 2011 Installed as FED 703 Installed as FED 727	9/10/2012	OK
2131	FED_721	8 May 2012: Removed from FED 720 for spurious reasons (red herring): eLog entry 8 May 2012: Installed back in as FED 721 since the power cycle of previous intervention fried DRAM on 721 eLog Entry	5/10/2012	OK
2132	904 Hospital	23 Jan 2012: Removed because we were not receiving any events over VME in local run. Possible software issue: http://cmsonline.cern.ch/cms-elog/750159	23 Jan 2012	Sick
2133	904 Hospital	Removed due to CRC errors during intervention on other DCC issues. Suspect spurious issue: http://cmsonline.cern.ch/cms-elog/637389 31 Jan 2012: Fails LRB memory test on LRB2, LRB3. Repaired, test ok 2012-03-06	31 Jan 2012	OK
2134	BU	Returned to BU because of alleged mis-matches	5/26	Sick
2135	FED_724	Tested. HTR13 LED broken. Now fixed.	5/26	OK
2136	BU	Shipped back to BU 6/9/09 per dick	to CERN 5/26	OK
2137	FED_725	Tested. Initially 2 errors. 2nd time tested-no errors. Probably a wiring issue.	5/26	OK
2138	FED_726	Tested.	5/26	OK
2139	FED_730	Installed on 3 Aug 2011 http://cmsonline.cern.ch/cms-elog/637389 Developed memory issues on LRB0 (sp 0,1,2) during Dec 2011 shutdown. Removed on 24 Jan 2012: http://cmsonline.cern.ch/cms-elog/750642 Fixed	3 Aug 2011	OK
2140	FED_728	Tested. Initially 2 errors. 2nd time tested-no errors. Probably a wiring issue.	5/26	OK
2141	FED_723	Tested.	5/26	OK
2142	904 Hospital	Prior incident as different FED (3/24/10): Was removed when we had an issue where no HTRs were sending data. No other symptoms point to DCC failure. Removed on 10 May 2012 due to LRB DRAM failure: eLog Entry	9/10/12	BAD LRB
2143	FED_718	Tested. Ethernet error(RJ 45). Was not fixed. Returned to BU 6/9/09. Tested/shipped back to CERN 23 Jan 2012: Installed as FED 718 http://cmsonline.cern.ch/cms-elog/750159	23 Jan 2012	OK
2144	904 Spares	16 Nov 2012: Removed due to LRB DRAM issue: eLog Entry. Not sure why we didn't address this guy over the winter 24 Oct 2012: Tested AOK after DRAM replacement eLog Entry	10/24/12	OK
2145	FED_703	"Stops sending events down SLINK and goes to OFW at 80 kHz" . Tested OK by PDL 4/1/11	11/16	OK
2146	BU	Tested. Pin9 of HTR14 RJ45 to U14 line open. Could be a PCB problem.		Sick
2147	BU	Tested. Two broken LEDs, Ethernet error(RJ 45), and CRC error. R25 cold solder,D25 is also missing. Errors fixed as of 6/3		OK
2148	904 Hospital	8 May 2012: Failed DRAM post power cycle at P5: eLog Entry pseudo-random data not changing; test probably failed Errors: LRB3	9/10/2012	BAD LRB
2149	BU	Tested. U0 soldering problem(most likely because U10 looks OK) Multiple lines to U10 without connection		Sick
2150	904 Hospital	Developed memory problems on LRB2 (spigots 6,7,8) during the Dec 2011 shutdown: http://cmsonline.cern.ch/cms-elog/750642. Repaired, test ok 2012-03-06	24 Jan 2012	OK
2151	FED_712	Tested.	6/1 OK
2152	FED_714	CRC Errors in Event Builder but not LRB. All errors from single LRB chip. See details below While it would be good to run the memory test on this guy, the symptoms are not classic DRAM failure http://cmsonline.cern.ch/cms-elog/402680 31 Jan 2012: Passes LRB, DSP memory tests in 904. Good board? Worth testing at P5	6/11/2010	Good
2153	FED_720	Developed memory problems on LRB3 (sp 9,10,11) during Dec 2011 shutdown. Removed on 24 Jan 2012 http://cmsonline.cern.ch/cms-elog/750642. Repaired, test ok 2012-03-06 8 May 2012 Installed as FED 720 at P5	24 Jan 2012	OK
2154	FED_704	Installed on 12 Jul 2011	12 Jul 2011	OK
2155	FED_729	Installed on 3 Aug 2011 http://cmsonline.cern.ch/cms-elog/637389	3 Aug 2011	OK
2156	904 Hospital	Tested.	6/1	sick? not in latest P5 scan
2157	*CERN	Tested. Warped board	6/1	OK/warped
2158	BU	Problem: DSP FW version 0x301c reports as version 0x0 on this board. Can program manually with DCC2Tool.exe w/o issues. CRC of DSP FW reported by DCC2Tool.exe is correct.	6/1 (returned)	Sick
2159	904 Hospital	Tested. 8/18/11 fail LRB4 test, however, this LRB is not in use (no spigots attached to HTRs) Developed memory issues on LRB1 (sp 3,4,5) over Dec 2011 shutdown. Removed on 24 Jan 2012: http://cmsonline.cern.ch/cms-elog/750642 Now LRB1 and LRB4 bad. Repaired, test ok 2012-03-06	24 Jan 2012	OK
2160	904 Spares	Removed from FED 700 due to UERR on spigot 13 - 10/29/09. 27 Jan 2012: Cannot reproduce UErrs on lxcmdtest3 while running at 83 kHz. Board looks good	27 Jan 2012	Ok
2161	FED_708	Tested.	6/1	OK
2162	FED_715	3 Aug 2011: Removed because it is not sending events over VME. Perhaps DAQ software issue? http://cmsonline.cern.ch/cms-elog/637389 26 Jan 2012: Tested on cmsmoe4 in 904. VME readout works just fine. Returning to pile of good spares	26 Jan 2012	OK
2163	BU	DDR memory chip replaced	2 Aug 2011	OK
2164	FED_715	Tested.	6/9	OK
2165	FED_711	Tested.	6/9	OK
2166	FED_731	Tested.	6/9	OK
2167	BU	Tested. Spigot CRC error/SLINK error		Sick
2168	FED_707	Tested.	6/9	OK
2169	FED_706	Tested.	6/9	OK
2170	BU	Tested. CRC errors. Spigot zero bad?		Sick
2171	FED_717	Tested.	6/9	OK
2172	904 Hospital	CRC errros on LRB FPGA serving spigots 12,13,14. Elog: http://cmsonline.cern.ch/cms-elog/605813 Replaced LRB4 @ CERN shop. All FW in FLASH except VME FW corrupted. Now fails memory test on LRB2? Elog: http://cmsonline.cern.ch/cms-elog/689158	5 Oct 2011	Sick: bad memory
2173	904 Hospital	CRC errors from LRB FPGA serving spigots 9,10,11. Elog: http://cmsonline.cern.ch/cms-elog/753520 Failes memory test on LRB3. Repaired, test ok 2012-03-06	24 Feb 2012	OK
2174	FED_702	Tested.	6/9	OK
2175	CERN	Tested. Broken LED-->VME. Declared good, shipped to CERN	8/18/11	OK
2176	904 Hospital	31 July 2011: Removed from FED 703 due to BcN mismatch problems. This occurred during ramping and is likely not an actual DCC issue: http://cmsonline.cern.ch/cms-elog/631675 3 Aug 2011: Installed as FED 727 http://cmsonline.cern.ch/cms-elog/637389 2 Mar 2012: Removed due to DRAM failure (LRB2) eLog Entry	9/10/2012	BAD LRB
2177	FED_709	Tested.	7/1	OK
2178	FED_705	Tested. Installed to replace 2160 - 10/29/09 10 May 2012: Installed as FED 705 to replace DCC with bad memoery.	9/10/12	OK
2179	FNAL	Tested.	Ship to FNAL 2011-05-12	OK
2180	BU	Tested. TTS link error. SLINK error.		Sick
2181	FED_700	CRC erros and "miscellaneous errors" during intervention on a different DCC problem: http://cmsonline.cern.ch/cms-elog/637389 Was eventually tested for bad memory and failed memory test. This appears to have developed memory issue during the aforementioned intervention 26 Jan 2012: This board had the affected LRB chip replaced at the CERN e-shop. Today it tested AOK at 904. Back to pile of spares	26 Jan 2012	OK
2182	FED_722	16 Nov 2012: Installed at P5 eLog Entry	9/10/2012	OK
2183	BU	Tested.	Ship to MN 2011-05-12	OK
2184	BU	Tested. CRC error, SLINK error. "event size of 4800 words is unreasonable"		Sick
2185	FED_713	Tested. Shipped to CERN on 8/18/11 Installed as FED 713 on 24 Jan 2012: http://cmsonline.cern.ch/cms-elog/750642	24 Jan 2012	OK
2186	FED_710	Tested. Shipped to CERN on 8/18/11 Installed as FED 710 on 24 Jan 2012: http://cmsonline.cern.ch/cms-elog/750642	24 Jan 2012	OK
2187	BU	Board is warped. won't fit into crate.		Sick
2188	BU	Tested. Ethernet RJ45 error.		Sick
2189	FED_716	Tested. Shipped to CERN on 8/18/11 Installed as FED 716 on 24 Jan 2012 http://cmsonline.cern.ch/cms-elog/750642	24 Jan 2012	OK
2190	CERN	Tested.	1/10	OK
2191	CERN	Tested.	1/10	OK
2192	CERN	Tested.	1/10	OK
2193	BU	Returned ~3/10/10 w/ spigot 3 problem (CASTOR)	1/10	Sick
2194	BU	Tested.	3/11/11 -- problems with spigots 3-5 (Eric/Dick)	Sick
2195	FED_719	Tested. Shipped to CERN 8/18/11 Installed as FED 719 on 24 Jan 2012: http://cmsonline.cern.ch/cms-elog/750642	8/18/11	OK
2196	CERN	Tested. Shipped to CERN	8/18/11	OK
2197	BU	Tested.		OK - retested@BU 11/19/12 with Charlie
2198	BU	Not ever tested?		?

Changes:

Updated 2144 which passed tests after DRAM replacement

-- PhilLawson - 24 Oct 2012

Updated to match latest round of spares installed. List of S/N installed in P5 is correct, not sure all other information is up to date.

-- EricHazen - 20 Sep 2012

For completeness, I would like to paste this here:

  FED  Crate  Slot  Serial     DSP     VME     LRB0     LRB1     LRB2     LRB3     LRB4
=======================================================================================
  700      4    10    2181  0x3027   0x106    0x110    0x110    0x110    0x110    0x110
  701      4    20    2001  0x3027   0x106    0x110    0x110    0x110    0x110    0x110
  702      0    10    2174  0x3027   0x106    0x110    0x110    0x110    0x110    0x110
  703      0    20    2145  0x3027   0x106    0x110    0x110    0x110    0x110    0x110
  704      1    10    2154  0x3027   0x106    0x110    0x110    0x110    0x110    0x110
  705      1    20    2178  0x3027   0x106    0x110    0x110    0x110    0x110    0x110
  706      5    10    2169  0x3027   0x106    0x110    0x110    0x110    0x110    0x110
  707      5    20    2168  0x3027   0x106    0x110    0x110    0x110    0x110    0x110
  708     11    10    2161  0x3027   0x106    0x110    0x110    0x110    0x110    0x110
  709     11    20    2177  0x3027   0x106    0x110    0x110    0x110    0x110    0x110
  710     15    10    2186  0x3027   0x106    0x110    0x110    0x110    0x110    0x110
  711     15    20    2165  0x3027   0x106    0x110    0x110    0x110    0x110    0x110
  712     17    10    2151  0x3027   0x106    0x110    0x110    0x110    0x110    0x110
  713     17    20    2185  0x3027   0x106    0x110    0x110    0x110    0x110    0x110
  714     14    10    2156  0x3027   0x106    0x110    0x110    0x110    0x110    0x110
  715     14    20    2164  0x3027   0x106    0x110    0x110    0x110    0x110    0x110
  716     10    10    2189  0x3027   0x106    0x110    0x110    0x110    0x110    0x110
  717     10    20    2171  0x3027   0x106    0x110    0x110    0x110    0x110    0x110
  718      2    10    2143  0x3027   0x106    0x110    0x110    0x110    0x110    0x110
  719      2    20    2195  0x3027   0x106    0x110    0x110    0x110    0x110    0x110
  720      9    10    2153  0x3027   0x106    0x110    0x110    0x110    0x110    0x110
  721      9    20    2131  0x3027   0x106    0x110    0x110    0x110    0x110    0x110
  722     12    10    2182  0x3027   0x106    0x110    0x110    0x110    0x110    0x110
  723     12    20    2141  0x3027   0x106    0x110    0x110    0x110    0x110    0x110
  724      3    10    2135  0x3027   0x106    0x110    0x110    0x110    0x110    0x110
  725      3    20    2137  0x3027   0x106    0x110    0x110    0x110    0x110    0x110
  726      7    10    2138  0x3027   0x106    0x110    0x110    0x110    0x110    0x110
  727      7    20    2130  0x3027   0x106    0x110    0x110    0x110    0x110    0x110
  728      6    10    2140  0x3027   0x106    0x110    0x110    0x110    0x110    0x110
  729      6    20    2155  0x3027   0x106    0x110    0x110    0x110    0x110    0x110
  730     13    10    2129  0x3027   0x106    0x110    0x110    0x110    0x110    0x110
  731     13    20    2166  0x3027   0x106    0x110    0x110    0x110    0x110    0x110

Update to log swap of 2176 -> 2130 -- PhilLawson - 10 Sep 2012

Update to reflect old swap of 2144->2182 -- PhilLawson - 10 Sep 2012

Update to reflect swap of 2148->2131 due to memory failure on 2148 -- PhilLawson - 10 Sep 2012

Update to reflect unnecessary swap of 2131->2153 -- PhilLawson - 10 Sep 2012

Update to reflect switch of 2178 -> 2142 on 10 May 2012 -- PhilLawson - 10 Sep 2012

SN 2173, 2159, 2133, 2153, 2150 tested after repair -- EricHazen - 06 Mar 2012

SN 2173 fails at P5. Tested with DCC2Tool.exe and it fails LRB3. Replaced with SN 2142 as FED 705. -- PhilLawson - 24 Feb 2012

SN 2133 fails memory test on LRB2, LRB3 Changes at P5: http://cmsonline.cern.ch/cms-elog/751963 -- PhilLawson - 31 Jan 2012

SN 2145 re-checked for SLINK integrity w/ fedkit. AOK. We should install this one @ P5 to be verified with MWGR before 2012 data taking

SN 2150 fails memory test on LRB2. This matches the symptoms of the spigots that were not working at P5.

SN 2160 Tests fine on lxcmdtest3 @ 43 kHz. Then we run again at 83 kHz (no TTS), HTRs are giving single bit errors which are corrected by DCC, but no UErrs show up on spigot 13 (this was the failure mode at P5). Returning to pile of good spares. Instrumented with cables to connect scope probes to monitor 3.3V and 2.5V supplies. Need to test at P5 in fully occupied crate to look for transient spikes.

SN 2132 retest VME readout. Still does not work.

-- PhilLawson - 27 Jan 2012

SN 2132 Tested on cmsmoe4 in 904. VME readout does not appear to work. xDAQ stops after 100 events (this is how many trigger credits are issued). Event Builder hyperdaq does not show any events coming in from the DCC's FED. Wu looks at register dump and states that it appears as if the VME spy buffer was already read out. Did the events get "dropped" in software? Why only for this board? Unclear. Needs further investigation.

SN 2162 Tested on cmsmoe4 in 904. VME readout works just fine. Returning to pile of good spares

SN 2181 checks out AOK with xDAQ run on lxcmdtest3 post replacement of LRB1 (U11)

Confirmed that 2153 has bad LRB3 memory

-- PhilLawson - 26 Jan 2012

Much eLog sifting to bring list up to date:

-- PhilLawson - 25 Jan 2012

S/N 2159 fails LRB4 link/memory test in the pit as FED 713. PDL discovered that these spigots are not in use on this FED and opted not to swap out.

-- EricHazen - 18 Aug 2011

S/N2163 LRB0 memory chip replaced. OK now. -- Main.Shouxiang Wu - 2 Aug 2011

S/N 2172 showed CRC errors on LRB FPGA serving spigots 12,13,14. Replaced in USC on 12 Jul 2011. Installed in 904 and powered up to find all LRB chips reporting appropriate FW versions.

-- PhilLawson - 19 Jul 2011

Ship 2179 and 2183 to FNAL and MN, respectively. Track# 1Z0159190193593478 and 1Z0159190190690681

-- EricHazen - 12 May 2011

Phil tested SN 2145 at CERN as follows:

Installed HCAL DAQ version 10.4.6 (unrelated, needed for different test)
Altered FedkitTest_LTClistenToTTS_from_slot20 to take SLINK data from slot 20.
Blasted high rate events at DCC. Due to SLINK readout (with only CRC error checking), 
  effective rate was limited to 34 kHz since this DCC was providing TTS signal.
Readout 10E6 events at this rate with no SLINK errors. Good enough for me.

-- PhilLawson - 24 Jan 2012

• Replaced line for 2151. This was accidentally removed during an edit a long while back. Good thing for twiki history!

-- EricHazen - 01 Apr 2011

• SN 2163 showed CRC errors on LRB chip serving spigots 0,1,2
  • SN 2177 installed in place as FED 709
  • Details in eLog: http://cmsonline.cern.ch/portal/page/portal/CMS%20online%20system/Elog?_piref815_429145_815_429142_429142.strutsAction=%2FviewMessageDetails.do%3FcatId%3D3%26subId%3D9%26msgId%3D468995

-- PhilLawson - 26 Jan 2011

• Updated list to reflect install of SN 2141 as FED 701 to replace sick DCC SN 2152.
  • SN 2152 evidenced communication problems between LRB and Event Builder chip
  • Details in eLog: 402680 on June 7 2010

-- PhilLawson - 11 Jun 2010

• Updated list to reflect swap of SN 2142 as FED 727

-- PhilLawson - 13 Apr 2010

• Updated list per inventory from Dick. Location with * were confirmed at CERN per Dick's 12/14/09 inventory.

-- EricHazen - 14 Dec 2009

• Check and update a few mistakes in the list of installed DCC2

-- EricHazen - 11 Dec 2009

• FED 719 (S/N 2145) was consistently going to OFW at 80 kHz. No events being sent down SLINK. Replaced DCC with S/N 2150

-- PhilLawson - 16 Nov 2009

• Logged in today and found FED 700 is now S/N 2160 (was previously 2001), FED 701 is now S/N 2152 (was previously 2002)
• Problem with FED 710 & DSP FW 0x301c described above.

-- PhilLawson - 26 Aug 2009