(r53) DCC2BoardDatabase < BUCMSPublic

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10 Prototype boards with red front panels were manufactured in early 2009.  These boards are _not identical_ to
the production boards  because they have a smaller FPGA.  The production front panels are marked "DCC2" and are black.

Boards are numbered in decimal starting with 2001 for the first prototype up to a maximum possible number of 2255.
The first digit is always '2'.  The other three digits represent the decimal equivalent of the binary value set by cutting jumpers
on the PCB.

You can find out which board is where in the pit as follows:

(log on to a head node, i.e. cmsusr1 etc)
<pre>
$ cd ~ehazen/GetStatus
$ ./getAllVersions.sh | ./parseVersions.pl

 Crate  Bus    Slot   Xilinx     LRB        VME    S/N  FED
 ====================================
     4  caen:0 10     0x3018     0x010a     0x0104 2001 700
     4  caen:0 20     0x3018     0x010a     0x0104 2002 701
     0  caen:1 10     0x3018     0x010a     0x0104 2174 702
     0  caen:1 20     0x3018     0x010a     0x0104 2176 703
       .... remainder of list truncated ...
</pre>

Here is [[http://cmsdoc.cern.ch/cms/HCAL/document/904/database/DCC/DCC2_database.htm][Dick Kellogg's list]] which may become
the official one.  For now, you have to check both.

---++ Prototype Boards

| *S/N* | *Location* | *Notes* |
| 2001 | 904 | Tested in MWGR 15 |
| 2002 | 904 | |
| 2003 | 904 | |
| 2004 | 904 | |
| 2005 | BU - Test stand | |
| 2006 | Whitman | To be destructively tested for soldering temperature profiles |
| 2007 | BU | Ethernet resistor replaced - re-test |
| 2008 | BU | Ethernet resistor replaced - re-test |
| 2009 | BU | Tested. No errors|
| 2010 | BU | |

---++ Production Boards

The production board serial numbers start with 2129 as shown below.
On the PCB, the binary "jumpers" (actually cut traces) start with "10000001".

Note that you can sort the table below by clicking the column headings.
Sort by *Location* for an easy way to check how many boards are where.

| *S/N* | *Location* | *Notes* |*Date shipped* | *Status* |
| 2129 | FED_730 | Tested.| 5/26| OK |
| 2130 | FED_703 | 1 July 2009: Orbit number mismatches as FED 731 (removed)<br> 31 July 2011 Installed as FED 703 | 31 July 2011 | OK |
| 2131 | FED_720 | Tested.| 5/26| OK |
| 2132 | 904 Hospital | 23 Jan 2012: Removed because we were not receiving any events over VME in local run. Possible software issue: http://cmsonline.cern.ch/cms-elog/750159 | 23 Jan 2012 | Sick |
| 2133 | 904 Hospital | Removed due to CRC errors during intervention on other DCC issues. Suspect spurious issue: http://cmsonline.cern.ch/cms-elog/637389 | 3 Aug 2011 | OK |
| 2134 | BU | Returned to BU because of alleged mis-matches | 5/26| Sick |
| 2135 | FED_724 | Tested. HTR13 LED broken. Now fixed.| 5/26| OK |
| 2136 | BU | Shipped back to BU 6/9/09 per dick | to CERN 5/26| OK |
| 2137 | FED_725 | Tested. Initially 2 errors. 2nd time tested-no errors. Probably a wiring issue. | 5/26| OK |
| 2138 | FED_726 | Tested. | 5/26| OK |
| 2139 | 904 Hospital | Installed on 3 Aug 2011 http://cmsonline.cern.ch/cms-elog/637389 <br> Developed memory issues on LRB0 (sp 0,1,2) during Dec 2011 shutdown. Removed on 24 Jan 2012: http://cmsonline.cern.ch/cms-elog/750642 | 3 Aug 2011 | Sick: bad memory |
| 2140 | FED_728 | Tested. Initially 2 errors. 2nd time tested-no errors. Probably a wiring issue. | 5/26| OK |
| 2141 | FED_723 | Tested.| 5/26| OK |
| 2142 | FED_701 | Prior incident as different FED (3/24/10): Was removed when we had an issue where no HTRs were sending data. No other symptoms point to DCC failure| 6/11/10| OK |
| 2143 | FED_718 | Tested. Ethernet error(RJ 45). Was not fixed. Returned to BU 6/9/09. Tested/shipped back to CERN <br> 23 Jan 2012: Installed as FED 718 http://cmsonline.cern.ch/cms-elog/750159 | 23 Jan 2012 | OK |
| 2144 | FED_722 | Tested.| 5/26| OK |
| 2145 | 904 Spares | "Stops sending events down SLINK and goes to OFW at 80 kHz" .  Tested OK by PDL 4/1/11  | 11/16| OK |
| 2146 | BU | Tested. Pin9 of HTR14 RJ45 to U14 line open. Could be a PCB problem. |    | Sick |
| 2147 | BU | Tested. Two broken LEDs, Ethernet error(RJ 45), and CRC error. R25 cold solder,D25 is also missing. Errors fixed as of 6/3| | OK |
| 2148 | FED_721 | Tested.| 5/26| OK |
| 2149 | BU | Tested.  U0 soldering problem(most likely because U10 looks OK) Multiple lines to U10 without connection|  | Sick |
| 2150 | 904 Hospital | Developed memory problems on LRB2 (spigots 6,7,8) during the Dec 2011 shutdown: http://cmsonline.cern.ch/cms-elog/750642  | 24 Jan 2012 | Sick: bad memory |
| 2151 | FED_712 | Tested. |6/1 OK |
| 2152 |904 Hospital | CRC Errors in Event Builder but not LRB. All errors from single LRB chip. See details below <br> TODO: run memory test | 6/11/2010| Sick: bad memory |
| 2153 | 904 Hospital | Developed memory problems on LRB4 (sp 9,10,11) during Dec 2011 shutdown. Removed on 24 Jan 2012 http://cmsonline.cern.ch/cms-elog/750642 <br> Phil's notes show LRB0 as bad. RE-TEST THIS ONE | 24 Jan 2012 | Sick: bad memory |
| 2154 | FED_704 | Installed on 12 Jul 2011 | 12 Jul 2011 | OK |
| 2155 | FED_729| Installed on 3 Aug 2011 http://cmsonline.cern.ch/cms-elog/637389 | 3 Aug 2011 | OK |
| 2156 | FED_714 | Tested. | 6/1| OK |
| 2157 | *CERN | Tested. Warped board | 6/1| OK/warped |
| 2158 | BU | *Problem:* DSP FW version 0x301c reports as version 0x0 on this board. Can program manually with =DCC2Tool.exe= w/o issues. CRC of DSP FW reported by =DCC2Tool.exe= is correct. | 6/1 (returned)| Sick |
| 2159 | 904 Hospital | Tested.  *8/18/11 fail LRB4 test*, however, this LRB is not in use (no spigots attached to HTRs) <br> Developed memory issues on LRB1 (sp 3,4,5) over Dec 2011 shutdown. Removed on 24 Jan 2012: http://cmsonline.cern.ch/cms-elog/750642 Now LRB1 and LRB4 bad | 24 Jan 2012 | Sick: bad memory |
| 2160 | 904 Hospital | Removed from FED 700 due to UERR on spigot 13 - 10/29/09. | 6/1| Sick |
| 2161 | FED_708 | Tested. | 6/1| OK |
| 2162 | 904 Hospital | 3 Aug 2011: Removed because it is not sending events over VME. Perhaps DAQ software issue? http://cmsonline.cern.ch/cms-elog/637389 | 6/1| OK |
| 2163 | BU | DDR memory chip replaced | 2 Aug 2011 | OK |
| 2164 | FED_715 | Tested. |6/9| OK |
| 2165 | FED_711 | Tested. |6/9| OK |
| 2166 | FED_731 | Tested. |6/9| OK |
| 2167 | BU | Tested. Spigot CRC error/SLINK error |      | Sick |
| 2168 | FED_707 | Tested. |6/9| OK |
| 2169 | FED_706 | Tested. |6/9| OK |
| 2170 | BU | Tested. CRC errors. Spigot zero bad?|      | Sick |
| 2171 | FED_717 | Tested. |6/9| OK |
| 2172 | 904 Hospital | CRC errros on LRB FPGA serving spigots 12,13,14. Elog: http://cmsonline.cern.ch/cms-elog/605813<br> Replaced LRB4 @ CERN shop. All FW in FLASH except VME FW corrupted. Now fails memory test on LRB2? Elog: http://cmsonline.cern.ch/cms-elog/689158 | 5 Oct 2011 | Sick |
| 2173 | FED_705 | Tested. |6/9| OK |
| 2174 | FED_702 | Tested. |6/9| OK |
| 2175 | CERN | Tested. Broken LED-->VME. Declared good, shipped to CERN|  8/18/11    | OK |
| 2176 | FED_727 | 31 July 2011: Removed from FED 703 due to BcN mismatch problems. This occurred during ramping and is likely not an actual DCC issue: http://cmsonline.cern.ch/cms-elog/631675 <br> 3 Aug 2011: Installed as FED 727 http://cmsonline.cern.ch/cms-elog/637389 | 3 Aug 2011 | OK |
| 2177 | FED_709 | Tested. |7/1| OK |
| 2178 | FED_700 | Tested. Installed to replace 2160 - 10/29/09 |7/1| OK |
| 2179 | FNAL| Tested.| Ship to FNAL 2011-05-12     | OK |
| 2180 | BU | Tested. TTS link error. SLINK error. |      | Sick |
| 2181 | 904 Hospital | CRC erros and "miscellaneous errors" during intervention on a different DCC problem: http://cmsonline.cern.ch/cms-elog/637389  | 3 Aug 2011 | Sick |
| 2182 | *CERN | Tested.  |7/1| OK |
| 2183 | BU | Tested.  |  Ship to MN 2011-05-12    | OK |
| 2184 | BU | Tested. CRC error, SLINK error. "event size of 4800 words is unreasonable" |      | Sick |
| 2185 | FED_713 | Tested.  Shipped to CERN on 8/18/11 <br> Installed as FED 713 on 24 Jan 2012: http://cmsonline.cern.ch/cms-elog/750642 | 24 Jan 2012 | OK |
| 2186 | FED_710 | Tested. Shipped to CERN on 8/18/11 <br> Installed as FED 710 on 24 Jan 2012: http://cmsonline.cern.ch/cms-elog/750642 | 24 Jan 2012 | OK |
| 2187 | BU | Board is warped. won't fit into crate. |      | Sick |
| 2188 | BU | Tested. Ethernet RJ45 error.|      | Sick |
| 2189 | FED_716 | Tested. Shipped to CERN on 8/18/11 <br> Installed as FED 716 on 24 Jan 2012 http://cmsonline.cern.ch/cms-elog/750642 | 24 Jan 2012 | OK |
| 2190 | CERN | Tested.| 1/10 | OK |
| 2191 | CERN | Tested.| 1/10 | OK |
| 2192 | CERN | Tested.| 1/10 | OK |
| 2193 | BU | Returned ~3/10/10 w/ spigot 3 problem (CASTOR)| 1/10 | Sick |
| 2194 | BU | Tested.| 3/11/11 -- problems with spigots 3-5 (Eric/Dick) | Sick |
| 2195 | FED_719 | Tested. Shipped to CERN 8/18/11 <br> Installed as FED 719 on 24 Jan 2012: http://cmsonline.cern.ch/cms-elog/750642| 8/18/11 | OK |
| 2196 | CERN | Tested. Shipped to CERN| 8/18/11 | OK |
| 2197 | BU | Tested.| | OK |
| 2198 | BU | Not ever tested? | | ? |

Changes:

Much eLog sifting to bring list up to date:

-- Main.PhilLawson - 25 Jan 2012

S/N 2159 fails LRB4 link/memory test in the pit as FED 713.  PDL discovered that these spigots are not in use on this FED and opted not to swap out.

-- Main.EricHazen - 18 Aug 2011

S/N2163 LRB0 memory chip replaced. OK now.
-- Main.Shouxiang Wu - 2 Aug 2011

S/N 2172 showed CRC errors on LRB FPGA serving spigots 12,13,14. Replaced in USC on 12 Jul 2011. Installed in 904 and powered up to find all LRB chips reporting appropriate FW versions.

-- Main.PhilLawson - 19 Jul 2011

Ship 2179 and 2183 to FNAL and MN, respectively.
Track# 1Z0159190193593478 and 1Z0159190190690681

-- Main.EricHazen - 12 May 2011

Phil tested SN 2145 at CERN as follows:

<verbatim>
Installed HCAL DAQ version 10.4.6 (unrelated, needed for different test)
Altered FedkitTest_LTClistenToTTS_from_slot20 to take SLINK data from slot 20.
Blasted high rate events at DCC. Due to SLINK readout (with only CRC error checking), 
  effective rate was limited to 34 kHz since this DCC was providing TTS signal.
Readout 10E6 events at this rate with no SLINK errors. Good enough for me.
</verbatim>

-- Main.PhilLawson - 24 Jan 2012
   * Replaced line for 2151. This was accidentally removed during an edit a long while back. Good thing for twiki history!

-- Main.EricHazen - 01 Apr 2011

   * SN 2163 showed CRC errors on LRB chip serving spigots 0,1,2
      * SN 2177 installed in place as FED 709
      * Details in eLog: http://cmsonline.cern.ch/portal/page/portal/CMS%20online%20system/Elog?_piref815_429145_815_429142_429142.strutsAction=%2FviewMessageDetails.do%3FcatId%3D3%26subId%3D9%26msgId%3D468995

-- Main.PhilLawson - 26 Jan 2011

   * Updated list to reflect install of SN 2141 as FED 701 to replace sick DCC SN 2152.
      * SN 2152 evidenced communication problems between LRB and Event Builder chip
      * Details in eLog: 402680 on June 7 2010

-- Main.PhilLawson - 11 Jun 2010

   * Updated list to reflect swap of SN 2142 as FED 727

-- Main.PhilLawson - 13 Apr 2010

   * Updated list per inventory from Dick.  Location with * were confirmed at CERN per Dick's 12/14/09 inventory.

-- Main.EricHazen - 14 Dec 2009

   * Check and update a few mistakes in the list of installed DCC2

-- Main.EricHazen - 11 Dec 2009


   * FED 719 (S/N 2145) was consistently going to OFW at 80 kHz. No events being sent down SLINK. Replaced DCC with S/N 2150

-- Main.PhilLawson - 16 Nov 2009

   * Logged in today and found FED 700 is now S/N 2160 (was previously 2001), FED 701 is now S/N 2152 (was previously 2002)
   * Problem with FED 710 & DSP FW 0x301c described above.

-- Main.PhilLawson - 26 Aug 2009
Topic revision: r53 - 25 Jan 2012 - PhilLawson