10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.

Boards are numbered in decimal starting with 2001 for the first prototype up to a maximum possible number of 2255. The first digit is always '2'. The other three digits represent the decimal equivalent of the binary value set by cutting jumpers on the PCB.

You can find out which board is where in the pit as follows:

(log on to a head node, i.e. cmsusr1 etc)

$ cd ~hazen/GetStatus
$ ./getAllVersions.sh | ./parseVersions.pl

 Crate  Bus    Slot   Xilinx     LRB        VME    S/N  FED
 ====================================
     4  caen:0 10     0x3018     0x010a     0x0104 2001 700
     4  caen:0 20     0x3018     0x010a     0x0104 2002 701
     0  caen:1 10     0x3018     0x010a     0x0104 2174 702
     0  caen:1 20     0x3018     0x010a     0x0104 2176 703
       .... remainder of list truncated ...

Prototype Boards

S/N Location Notes
2001 USC FED 700 Tested in MWGR 15
2002 USC FED 701  
2003 CERN - Bat 28 - cmsmoe6  
2004 CERN - Bat 904 - cmsmoe4  
2005 BU - Test stand  
2006 Whitman To be destructively tested for soldering temperature profiles
2007 BU Ethernet resistor replaced - re-test
2008 BU Ethernet resistor replaced - re-test
2009 BU Tested. No errors
2010 BU  

Production Boards

The production board serial numbers start with 2129 as shown below. On the PCB, the binary "jumpers" (actually cut traces) start with "10000001".

S/N LocationSorted ascending Notes Date shipped
2143 BU Tested. Ethernet error(RJ 45). Was not fixed. Accidentally shipped 5/26
2146 BU Tested. Pin9 of HTR14 RJ45 to U14 line open. Could be a PCB problem.  
2147 BU Tested. Two broken LEDs, Ethernet error(RJ 45), and CRC error. R25 cold solder,D25 is also missing. Errors fixed as of 6/3
2149 BU Tested. U0 soldering problem(most likely because U10 looks OK) Multiple lines to U10 without connection
2167 BU Tested. Spigot CRC error/SLINK error  
2170 BU Tested. CRC errors. Spigot zero bad?  
2175 BU Tested. Broken LED-->VME.  
2179 BU Tested.  
2180 BU Tested. TTS link error. SLINK error.  
2183 BU Tested.  
2184 BU Tested. CRC error, SLINK error. "event size of 4800 words is unreasonable"  
2185 BU Tested.  
2186 BU Tested.  
2187 BU Board is warped. won't fit into crate.  
2188 BU Tested. Ethernet RJ45 error.  
2189 BU Tested.  
2190 BU Tested.  
2191 BU Tested.  
2192 BU Tested.  
2193 BU Tested.  
2194 BU Tested.  
2195 BU Tested.  
2196 BU Tested.  
2197 BU Tested.  
2130 CERN Tested. 5/26
2134 CERN Tested. 5/26
2136 CERN Tested. 5/26
2139 CERN Tested. 5/26
2150 CERN Tested. 7/1
2151 CERN Tested. 6/1
2152 CERN Tested. 6/1
2153 CERN Tested. 6/1
2154 CERN Tested. 6/1
2155 CERN Tested. 6/1
2157 CERN Tested. 6/1
2159 CERN Tested. 6/1
2160 CERN Tested. 6/1
2177 CERN Tested. 7/1
2178 CERN Tested. 7/1
2181 CERN Tested. 7/1
2182 CERN Tested. 7/1
2174 FED_702 Tested. 6/9
2176 FED_703 Tested. 6/9
2172 FED_704 Tested. 6/9
2173 FED_705 Tested. 6/9
2169 FED_706 Tested. 6/9
2168 FED_707 Tested. 6/9
2161 FED_708 Tested. 6/1
2163 FED_709 Tested. 6/1
2158 FED_710 Tested. 6/1
2165 FED_711 Tested. 6/9
2156 FED_714 Tested. 6/1
2164 FED_715 Tested. 6/9
2162 FED_716 Tested. 6/1
2171 FED_717 Tested. 6/9
2132 FED_718 Tested. 5/26
2145 FED_719 Tested. 5/26
2131 FED_720 Tested. 5/26
2148 FED_721 Tested. 5/26
2144 FED_722 Tested. 5/26
2141 FED_723 Tested. 5/26
2135 FED_724 Tested. HTR13 LED broken. Now fixed. 5/26
2137 FED_725 Tested. Initially 2 errors. 2nd time tested-no errors. Probably a wiring issue. 5/26
2138 FED_726 Tested. 5/26
2142 FED_727 Tested. 5/26
2140 FED_728 Tested. Initially 2 errors. 2nd time tested-no errors. Probably a wiring issue. 5/26
2133 FED_729 Tested. 5/26
2129 FED_730 Tested. 5/26
2166 FED_731 Tested. 6/9

EricHazen - 15 Apr 2009


This topic: BUCMSPublic > WebHome > DCC2Documentation > DCC2BoardDatabase
Topic revision: r17 - 09 Jul 2009 - EricHazen
 
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