We are now (November 2013) making a design change to the T2 board to improve the timing of the TTC clock vs data. The extracted TTC clock is sent on the MicroTCA clock network (received on FCLKA on an AMC card), while the data is sent as DC-coupled LVDS on fabric B (port 3 on an AMC card). The data is simply un-encoded 80 MB/s serial data with the TTC A/B channels alternating.

The original idea was that the timing would be well enough aligned at the source that a simple DDR register could receive it without any skew adjustment. It turned on in the prototype AMC13 (v1 and XG) that there is a large delay range in the M-LVDS driver chips used to launch the clock on the backplane. This results in troublesome timing adjustment required on the receiving end to reliably capture the TTC signal.

We have redesigned the clock fanout hardware slightly as described in this sketch: TTC_Clock_Skew_Adjust_Scheme.pdf.

This new topology allows for an individual phase tune of the fabric B data to match the measured delay in each M-LVDS chip (the channel-to-channel delay is small).

We expect to prototype this new design very soon and use it going forward.

-- EricHazen - 08 Nov 2013

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Topic revision: r1 - 08 Nov 2013 - EricHazen
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