ClockFanoutUpgrade < BUCMSPublic

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We have made a design change to the T2 board to improve
the timing of the TTC clock vs data.  The extracted TTC clock is sent on the MicroTCA
clock network (received on FCLKA on an AMC card), while the data is sent as
DC-coupled LVDS on fabric B (port 3 on an AMC card).  The data is simply un-encoded
80 MB/s serial data with the TTC A/B channels alternating.

The original idea was that the timing would be well enough aligned at the source
that a simple DDR register could receive it without any skew adjustment.
It turned on in the prototype AMC13 (v1 and XG) that there is a large delay range
in the M-LVDS driver chips used to launch the clock on the backplane.  This results
in troublesome timing adjustment required on the receiving end to reliably capture
the TTC signal.

We have redesigned the clock fanout hardware slightly as described in this sketch:
[[http://ohm.bu.edu/~hazen/CMS/TTC_Clock_Skew_Adjust_Scheme.pdf][TTC_Clock_Skew_Adjust_Scheme.pdf]].

This new topology allows for an individual phase tune of the fabric B data to match
the measured delay in each M-LVDS chip (the channel-to-channel delay is small).

We have just now (March 2014) received a run of prototype boards with the new scheme.

-- Main.EricHazen - 11 Mar 2014
Topic revision: r2 - 11 Mar 2014 - EricHazen