Please see AMC13BackplaneLink for current information.

Here are some notes on the DAQ interface (implemented here: 2012-01-21 Firmware) in late 2011 for HCAL testing. All is subject to change!

The current AMC13 design uses an Xilinx XC6VLX130T-FF1156-1C part (the -1 is the speed grade). The GTX transceivers in this part support a maximum rate of 5.0Gb/s, though we have tested them somewhat higher (5.2, I believe) without error. ("without error" means ~5e15 bits through a 30m fiber with PRBS check). The faster speed grades (-2 and -3) support up to 6.6Gb/sec.

We have in hand 10 boards with the speed grade -1 so we should settle on 5.0Gb/sec for the first generation.

We have a current demonstration protocol which is rather simple, and still unfortunately not documented in detail. However, here is my attempt to describe it. Perhaps Mr Wu will correct any gross errors (he is in China but in intermittent e-mail contact):

Data is transmitted in 4kB maximum size packets using currently 8b/10b coding and packet framing and checksum similar to GbE (but not GbE protocol). The transmitter expects an ACK from the receiver for each packet after twice the fiber delay plus serdes latency. The transmitter keeps a short buffer of transmitted packets (currently 4) awaiting ACK. Each packet has an ACK timer, and if the timer expires the transmitter starts sending again beginning with the first packet awaiting ACK.

For a 100m fiber at even 10Gb/sec, only four 4k byte buffers are required for retransmit, and this buffer space can easily be accommodated in on-board FPGA RAM.

The data format in our prototype link is essentially identical to the CMS common data format, with the same format 64-bit header and trailer words. Network byte order (MSB first) is used for 64-bit words. The payload is counted in 32-bit words, padded if necessary to a 64-bit boundary.

Event fragments begin and end on packet boundaries. A unique EOF_word (control word) marks the end of an event fragment.

We have a firmware implementation with the transmitter (LSC) and receiver (LDC) implemented in VHDL and tested on Xilinx Virtex-6 and Spartan-6 devices at 5Gb/s. When Mr Wu returns after the holiday (January 3rd) we can send you the code so that you can consider porting the receiver to your Altera-based test board.

We are considering the options for a 10Gb/s design. Clearly one option is to use a SERDES ASIC such as you have done. One reason why this is not a drop-in on our current design is that we do not have the four MGT ports to support it on the FPGA, and it would require a significant redesign. Another option is to use an FPGA which supports 10Gb/s directly (fastest Xilinx Virtex-6 or a -7 series). This is also a significant redesign.

When we make the transition to 10Gb/s we would change the protocol a bit, at least to 64B/66B coding as used in 10GbE. We would prefer to keep the low-level protocol a simple one such as described above.

-- EricHazen - 21 Jan 2012

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Topic revision: r2 - 15 Jul 2014 - EricHazen
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