0x24a has implemented the double buffering of monitor counters.
Registers 0x0, 0x3, 0x4, 0x5, 0x2c and
0x30-0x59(resync counter has been moved from
bit 31-16 of register 0x1a to reg 0x58 and 0x59)
Have been double buffered.
The TTC command for double buffer has been temporarily
defaulted as 0x68, it can be reprogrammed with reg 0x2d
It can also be initiated by writing 0x200 to reg 0x0 for test
Since a lot of codes related to counters have been rewritten,
even though the first check looked OK, could someone have
a further check to make sure the counters are still in the right
place and counting correctly.
The double buffer area has an offset of 0x8000, i.e., always have
ipbus2 address bit 15 set.
SN161 has 0x24a programmed at the moment, the mcs file is
also available. The spec file has not been updated to avoid confusion.


-- EricHazen - 06 Mar 2016

Topic revision: r1 - 06 Mar 2016 - EricHazen
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