Difference: DTCDesign (1 vs. 18)

Revision 1807 Jul 2010 - EricHazen

Line: 1 to 1
 
META TOPICPARENT name="CmsSlhc"
We are designing a microTCA module called the DTC (DAQ and Timing Card) for the HCAL SLHC readout. It is currently envisioned that this will occupy one of the MCH slots in a dual-star type crate.
Line: 8 to 8
 DTCDebugLog – Please log all significant test activity here

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Revision 1706 Jul 2010 - EricHazen

Line: 1 to 1
 
META TOPICPARENT name="CmsSlhc"
We are designing a microTCA module called the DTC (DAQ and Timing Card) for the HCAL SLHC readout. It is currently envisioned that this will occupy one of the MCH slots in a dual-star type crate.
Line: 8 to 8
 DTCDebugLog – Please log all significant test activity here

Added:
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Revision 1615 Jun 2010 - EricHazen

Line: 1 to 1
 
META TOPICPARENT name="CmsSlhc"
We are designing a microTCA module called the DTC (DAQ and Timing Card) for the HCAL SLHC readout. It is currently envisioned that this will occupy one of the MCH slots in a dual-star type crate.
Line: 16 to 16
 
Changed:
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Revision 1510 Jun 2010 - EricHazen

Line: 1 to 1
 
META TOPICPARENT name="CmsSlhc"
We are designing a microTCA module called the DTC (DAQ and Timing Card) for the HCAL SLHC readout. It is currently envisioned that this will occupy one of the MCH slots in a dual-star type crate.
Line: 7 to 7
  DTCDebugLog – Please log all significant test activity here
Added:
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Revision 1418 Mar 2010 - EricHazen

Line: 1 to 1
 
META TOPICPARENT name="CmsSlhc"
We are designing a microTCA module called the DTC (DAQ and Timing Card) for the HCAL SLHC readout. It is currently envisioned that this will occupy one of the MCH slots in a dual-star type crate.
Line: 8 to 8
 DTCDebugLog – Please log all significant test activity here

  • MicroTCASoftware – Software to support talking to AMCs via MCH: RMCP, IPMI etc
Added:
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>
 
  • DTC_SPecification.pdf – preliminary description – updated 5/17.09
  • PICMG standards – EDF only: username / password required
  • Documentation for CorEdge mini uTCA systems we have 2 of

Revision 1326 Jan 2010 - EricHazen

Line: 1 to 1
 
META TOPICPARENT name="CmsSlhc"
We are designing a microTCA module called the DTC (DAQ and Timing Card) for the HCAL SLHC readout. It is currently envisioned that this will occupy one of the MCH slots in a dual-star type crate. Initially we would build cards for MCH connectors 1 and 2, providing clock distribution on finger 2, and fast controls and trigger feedback on port 1 of fabric A on finger 1.
Added:
>
>
DTCDebugLog – Please log all significant test activity here
 

Revision 1225 Jan 2010 - EricHazen

Line: 1 to 1
 
META TOPICPARENT name="CmsSlhc"
We are designing a microTCA module called the DTC (DAQ and Timing Card) for the HCAL SLHC readout. It is currently envisioned that this will occupy one of the MCH slots in a dual-star type crate. Initially we would build cards for MCH connectors 1 and 2, providing clock distribution on finger 2, and fast controls and trigger feedback on port 1 of fabric A on finger 1.
Added:
>
>
  • MicroTCASoftware – Software to support talking to AMCs via MCH: RMCP, IPMI etc
 
  • DTC_SPecification.pdf – preliminary description – updated 5/17.09
  • PICMG standards – EDF only: username / password required
  • Documentation for CorEdge mini uTCA systems we have 2 of

Revision 1123 Jan 2010 - EricHazen

Line: 1 to 1
 
META TOPICPARENT name="CmsSlhc"
We are designing a microTCA module called the DTC (DAQ and Timing Card) for the HCAL SLHC readout. It is currently envisioned that this will occupy one of the MCH slots in a dual-star type crate.
Line: 32 to 32
  On the CTR2 FCLKA, TCLKA and TCLKC all enter an SN65LVDT125A LVDS crosspoint switch, and from there can be routed to the FPGA or links, possibly via an Si5319 frequency synthesizer.
Changed:
<
<
Also, MiniCTR2 connects to ports 0, 1, 8 with GTX.
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>
Also, MiniCTR2 connects to ports 0, 1, 8 with GTX. All other ports are connected to generic FPGA I/Os.
  Jeremy's requests: Transmit LHC clock on CLK1 or CLK3. TTC encoded stream on Fabric B Tx (port 2/3). TTS received on Fabric B Rx (port 2/3).
Changed:
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<
CorEdge mini crate backplane: Only CLK2, CLK3 routed. Fabric A-port 0. Fabric B-port 2. Fabrics D-G to ports 4-7.
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CorEdge mini crate backplane: Only CLK2, CLK3 routed. Fabric A to port 0. Fabric B to port 2. Fabrics D-G to ports 4-7.
 
Changed:
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Wu would prefer to send TTC on a fabric D-G because they are on T3. This should be OK for now but should maybe connect DTC to both?
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Wu would prefer to send TTC on a fabric D-G because they are on T3. Instead I think we should send them on fabric B.
 

Parts

Revision 1023 Jan 2010 - EricHazen

Line: 1 to 1
 
META TOPICPARENT name="CmsSlhc"
We are designing a microTCA module called the DTC (DAQ and Timing Card) for the HCAL SLHC readout. It is currently envisioned that this will occupy one of the MCH slots in a dual-star type crate.
Line: 9 to 9
 
Added:
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>
 
Added:
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Drawings

Line: 29 to 32
  On the CTR2 FCLKA, TCLKA and TCLKC all enter an SN65LVDT125A LVDS crosspoint switch, and from there can be routed to the FPGA or links, possibly via an Si5319 frequency synthesizer.
Changed:
<
<
It is challenging to understand the AMC and µTCA clocking. My current understanding is that dual-star backplanes typically fanout one clock from each MCH to each AMC, and return one clock from each AMC to either MCH.
>
>
Also, MiniCTR2 connects to ports 0, 1, 8 with GTX.
 
Changed:
<
<
Wu's current thoughts: Transmit TTC clock on Fabric B (port 2/3) Tx (MCH->AMC) pair, TTC data on other pair of Fabric B. But MiniCTR2 does not connect port B to clock-friendly inputs. So, maybe back to TTC clock on CLK1, TTC data on Fabric B?
>
>
Jeremy's requests: Transmit LHC clock on CLK1 or CLK3. TTC encoded stream on Fabric B Tx (port 2/3). TTS received on Fabric B Rx (port 2/3).
 
Changed:
<
<
Also, MiniCTR2 connects to ports 0, 1, 8 with GTX.
>
>
CorEdge mini crate backplane: Only CLK2, CLK3 routed. Fabric A-port 0. Fabric B-port 2. Fabrics D-G to ports 4-7.
 
Changed:
<
<
Jeremy's requests: Transmit LHC clock on CLK1 or CLK3. TTC encoded stream on Fabric B Tx (port 3/4). TTS received on Fabric B Rx (port 3/4).
>
>
Wu would prefer to send TTC on a fabric D-G because they are on T3. This should be OK for now but should maybe connect DTC to both?
 

Parts

Revision 922 Jan 2010 - EricHazen

Line: 1 to 1
 
META TOPICPARENT name="CmsSlhc"
We are designing a microTCA module called the DTC (DAQ and Timing Card) for the HCAL SLHC readout. It is currently envisioned that this will occupy one of the MCH slots in a dual-star type crate.
Line: 23 to 23
 
Type AMC Name μTCA Name Contacts Direction
Telecom TCLKA CLK1 74/75 In to AMC
Telecom TCLKB CLK2 77/78 Out from AMC
Changed:
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<
Telecom TCLKC CLK3 135/136 In to AMC
>
>
Telecom TCLKC   135/136 In to AMC
 
Telecom TCLKD   138/139 Out from AMC
Changed:
<
<
Fabric FCLKA   80/81 In to AMC
>
>
Fabric FCLKA CLK3 80/81 In to AMC
  On the CTR2 FCLKA, TCLKA and TCLKC all enter an SN65LVDT125A LVDS crosspoint switch, and from there can be routed to the FPGA or links, possibly via an Si5319 frequency synthesizer.
Line: 50 to 50
 
Deleted:
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-- EricHazen - 03 Oct 2009
 \ No newline at end of file
Added:
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-- EricHazen - 22 Jan 2010
 \ No newline at end of file

Revision 812 Nov 2009 - EricHazen

Line: 1 to 1
 
META TOPICPARENT name="CmsSlhc"
We are designing a microTCA module called the DTC (DAQ and Timing Card) for the HCAL SLHC readout. It is currently envisioned that this will occupy one of the MCH slots in a dual-star type crate.
Line: 33 to 33
  Wu's current thoughts: Transmit TTC clock on Fabric B (port 2/3) Tx (MCH->AMC) pair, TTC data on other pair of Fabric B. But MiniCTR2 does not connect port B to clock-friendly inputs. So, maybe back to TTC clock on CLK1, TTC data on Fabric B?
Changed:
<
<
Also, MiniCTR2 connects only to ports 0, 1 with GTX, so DAQ can't be on fat pipes (sigh).
>
>
Also, MiniCTR2 connects to ports 0, 1, 8 with GTX.

Jeremy's requests: Transmit LHC clock on CLK1 or CLK3. TTC encoded stream on Fabric B Tx (port 3/4). TTS received on Fabric B Rx (port 3/4).

 

Parts

Revision 709 Nov 2009 - EricHazen

Line: 1 to 1
 
META TOPICPARENT name="CmsSlhc"
We are designing a microTCA module called the DTC (DAQ and Timing Card) for the HCAL SLHC readout. It is currently envisioned that this will occupy one of the MCH slots in a dual-star type crate.
Line: 41 to 41
 
Added:
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MicroTCA Vendors

 -- EricHazen - 03 Oct 2009 \ No newline at end of file

Revision 606 Nov 2009 - EricHazen

Line: 1 to 1
 
META TOPICPARENT name="CmsSlhc"
We are designing a microTCA module called the DTC (DAQ and Timing Card) for the HCAL SLHC readout. It is currently envisioned that this will occupy one of the MCH slots in a dual-star type crate.
Line: 29 to 29
  On the CTR2 FCLKA, TCLKA and TCLKC all enter an SN65LVDT125A LVDS crosspoint switch, and from there can be routed to the FPGA or links, possibly via an Si5319 frequency synthesizer.
Changed:
<
<
It is challenging to understand the AMC and µTCA clocking. My current understanding is that dual-star backplanes typically fanout one clock from each MCH to each AMC, and return one clock from each AMC to either MCH. This implies to me that we should use the single clock as a fixed-frequency link clock and that the LHC clock should be embedded in the stream sent on fabric port 1 from the MCH to the AMCs.
>
>
It is challenging to understand the AMC and µTCA clocking. My current understanding is that dual-star backplanes typically fanout one clock from each MCH to each AMC, and return one clock from each AMC to either MCH.

Wu's current thoughts: Transmit TTC clock on Fabric B (port 2/3) Tx (MCH->AMC) pair, TTC data on other pair of Fabric B. But MiniCTR2 does not connect port B to clock-friendly inputs. So, maybe back to TTC clock on CLK1, TTC data on Fabric B?

Also, MiniCTR2 connects only to ports 0, 1 with GTX, so DAQ can't be on fat pipes (sigh).

 

Parts

Revision 526 Oct 2009 - EricHazen

Line: 1 to 1
 
META TOPICPARENT name="CmsSlhc"
We are designing a microTCA module called the DTC (DAQ and Timing Card) for the HCAL SLHC readout. It is currently envisioned that this will occupy one of the MCH slots in a dual-star type crate.
Line: 12 to 12
 
Added:
>
>

Drawings

  • MCH_MECHANICS.pdf – MCH board stack with component height restrictions. (ref uTCA standard p2-69 (117) and AMC.0 spec p2-25 (65)).
 

Design Thoughts

Clocking – per AMC spec:

Revision 426 Oct 2009 - EricHazen

Line: 1 to 1
 
META TOPICPARENT name="CmsSlhc"
We are designing a microTCA module called the DTC (DAQ and Timing Card) for the HCAL SLHC readout. It is currently envisioned that this will occupy one of the MCH slots in a dual-star type crate.
Line: 12 to 12
 
Changed:
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=Design Thoughts=
>
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Design Thoughts

  Clocking – per AMC spec:
Line: 27 to 27
  It is challenging to understand the AMC and µTCA clocking. My current understanding is that dual-star backplanes typically fanout one clock from each MCH to each AMC, and return one clock from each AMC to either MCH. This implies to me that we should use the single clock as a fixed-frequency link clock and that the LHC clock should be embedded in the stream sent on fabric port 1 from the MCH to the AMCs.
Added:
>
>

Parts

 -- EricHazen - 03 Oct 2009

Revision 318 Oct 2009 - EricHazen

Line: 1 to 1
 
META TOPICPARENT name="CmsSlhc"
We are designing a microTCA module called the DTC (DAQ and Timing Card) for the HCAL SLHC readout. It is currently envisioned that this will occupy one of the MCH slots in a dual-star type crate.
Line: 10 to 10
 
Added:
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>
 
Added:
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=Design Thoughts=

Clocking – per AMC spec:

Type
<-- -->
Sorted ascending
AMC Name μTCA Name Contacts Direction
Fabric FCLKA   80/81 In to AMC
Telecom TCLKA CLK1 74/75 In to AMC
Telecom TCLKB CLK2 77/78 Out from AMC
Telecom TCLKC CLK3 135/136 In to AMC
Telecom TCLKD   138/139 Out from AMC

On the CTR2 FCLKA, TCLKA and TCLKC all enter an SN65LVDT125A LVDS crosspoint switch, and from there can be routed to the FPGA or links, possibly via an Si5319 frequency synthesizer.

It is challenging to understand the AMC and µTCA clocking. My current understanding is that dual-star backplanes typically fanout one clock from each MCH to each AMC, and return one clock from each AMC to either MCH. This implies to me that we should use the single clock as a fixed-frequency link clock and that the LHC clock should be embedded in the stream sent on fabric port 1 from the MCH to the AMCs.

  -- EricHazen - 03 Oct 2009

Revision 216 Oct 2009 - EricHazen

Line: 1 to 1
 
META TOPICPARENT name="CmsSlhc"
We are designing a microTCA module called the DTC (DAQ and Timing Card) for the HCAL SLHC readout. It is currently envisioned that this will occupy one of the MCH slots in a dual-star type crate.
Line: 6 to 6
 and fast controls and trigger feedback on port 1 of fabric A on finger 1.

Changed:
<
<
>
>
 

-- EricHazen - 03 Oct 2009

Revision 103 Oct 2009 - EricHazen

Line: 1 to 1
Added:
>
>
META TOPICPARENT name="CmsSlhc"
We are designing a microTCA module called the DTC (DAQ and Timing Card) for the HCAL SLHC readout. It is currently envisioned that this will occupy one of the MCH slots in a dual-star type crate. Initially we would build cards for MCH connectors 1 and 2, providing clock distribution on finger 2, and fast controls and trigger feedback on port 1 of fabric A on finger 1.

-- EricHazen - 03 Oct 2009

 
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