Difference: DTCDesign (5 vs. 6)

Revision 606 Nov 2009 - EricHazen

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META TOPICPARENT name="CmsSlhc"
We are designing a microTCA module called the DTC (DAQ and Timing Card) for the HCAL SLHC readout. It is currently envisioned that this will occupy one of the MCH slots in a dual-star type crate.
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  On the CTR2 FCLKA, TCLKA and TCLKC all enter an SN65LVDT125A LVDS crosspoint switch, and from there can be routed to the FPGA or links, possibly via an Si5319 frequency synthesizer.
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It is challenging to understand the AMC and µTCA clocking. My current understanding is that dual-star backplanes typically fanout one clock from each MCH to each AMC, and return one clock from each AMC to either MCH. This implies to me that we should use the single clock as a fixed-frequency link clock and that the LHC clock should be embedded in the stream sent on fabric port 1 from the MCH to the AMCs.
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It is challenging to understand the AMC and µTCA clocking. My current understanding is that dual-star backplanes typically fanout one clock from each MCH to each AMC, and return one clock from each AMC to either MCH.

Wu's current thoughts: Transmit TTC clock on Fabric B (port 2/3) Tx (MCH->AMC) pair, TTC data on other pair of Fabric B. But MiniCTR2 does not connect port B to clock-friendly inputs. So, maybe back to TTC clock on CLK1, TTC data on Fabric B?

Also, MiniCTR2 connects only to ports 0, 1 with GTX, so DAQ can't be on fat pipes (sigh).

 

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