Difference: DTCDesign (2 vs. 3)

Revision 318 Oct 2009 - EricHazen

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META TOPICPARENT name="CmsSlhc"
We are designing a microTCA module called the DTC (DAQ and Timing Card) for the HCAL SLHC readout. It is currently envisioned that this will occupy one of the MCH slots in a dual-star type crate.
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=Design Thoughts=

Clocking – per AMC spec:

Type AMC Name μTCA Name Contacts Direction
Telecom TCLKA CLK1 74/75 In to AMC
Telecom TCLKB CLK2 77/78 Out from AMC
Telecom TCLKC CLK3 135/136 In to AMC
Telecom TCLKD   138/139 Out from AMC
Fabric FCLKA   80/81 In to AMC

On the CTR2 FCLKA, TCLKA and TCLKC all enter an SN65LVDT125A LVDS crosspoint switch, and from there can be routed to the FPGA or links, possibly via an Si5319 frequency synthesizer.

It is challenging to understand the AMC and µTCA clocking. My current understanding is that dual-star backplanes typically fanout one clock from each MCH to each AMC, and return one clock from each AMC to either MCH. This implies to me that we should use the single clock as a fixed-frequency link clock and that the LHC clock should be embedded in the stream sent on fabric port 1 from the MCH to the AMCs.

  -- EricHazen - 03 Oct 2009
 
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