Difference: DTCDesign (10 vs. 11)

Revision 1123 Jan 2010 - EricHazen

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META TOPICPARENT name="CmsSlhc"
We are designing a microTCA module called the DTC (DAQ and Timing Card) for the HCAL SLHC readout. It is currently envisioned that this will occupy one of the MCH slots in a dual-star type crate.
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  On the CTR2 FCLKA, TCLKA and TCLKC all enter an SN65LVDT125A LVDS crosspoint switch, and from there can be routed to the FPGA or links, possibly via an Si5319 frequency synthesizer.
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Also, MiniCTR2 connects to ports 0, 1, 8 with GTX.
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Also, MiniCTR2 connects to ports 0, 1, 8 with GTX. All other ports are connected to generic FPGA I/Os.
  Jeremy's requests: Transmit LHC clock on CLK1 or CLK3. TTC encoded stream on Fabric B Tx (port 2/3). TTS received on Fabric B Rx (port 2/3).
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CorEdge mini crate backplane: Only CLK2, CLK3 routed. Fabric A-port 0. Fabric B-port 2. Fabrics D-G to ports 4-7.
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CorEdge mini crate backplane: Only CLK2, CLK3 routed. Fabric A to port 0. Fabric B to port 2. Fabrics D-G to ports 4-7.
 
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Wu would prefer to send TTC on a fabric D-G because they are on T3. This should be OK for now but should maybe connect DTC to both?
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Wu would prefer to send TTC on a fabric D-G because they are on T3. Instead I think we should send them on fabric B.
 

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