Difference: DTCDesign (9 vs. 10)

Revision 1023 Jan 2010 - EricHazen

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META TOPICPARENT name="CmsSlhc"
We are designing a microTCA module called the DTC (DAQ and Timing Card) for the HCAL SLHC readout. It is currently envisioned that this will occupy one of the MCH slots in a dual-star type crate.
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  On the CTR2 FCLKA, TCLKA and TCLKC all enter an SN65LVDT125A LVDS crosspoint switch, and from there can be routed to the FPGA or links, possibly via an Si5319 frequency synthesizer.
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It is challenging to understand the AMC and µTCA clocking. My current understanding is that dual-star backplanes typically fanout one clock from each MCH to each AMC, and return one clock from each AMC to either MCH.
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Also, MiniCTR2 connects to ports 0, 1, 8 with GTX.
 
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Wu's current thoughts: Transmit TTC clock on Fabric B (port 2/3) Tx (MCH->AMC) pair, TTC data on other pair of Fabric B. But MiniCTR2 does not connect port B to clock-friendly inputs. So, maybe back to TTC clock on CLK1, TTC data on Fabric B?
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Jeremy's requests: Transmit LHC clock on CLK1 or CLK3. TTC encoded stream on Fabric B Tx (port 2/3). TTS received on Fabric B Rx (port 2/3).
 
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Also, MiniCTR2 connects to ports 0, 1, 8 with GTX.
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CorEdge mini crate backplane: Only CLK2, CLK3 routed. Fabric A-port 0. Fabric B-port 2. Fabrics D-G to ports 4-7.
 
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Jeremy's requests: Transmit LHC clock on CLK1 or CLK3. TTC encoded stream on Fabric B Tx (port 3/4). TTS received on Fabric B Rx (port 3/4).
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Wu would prefer to send TTC on a fabric D-G because they are on T3. This should be OK for now but should maybe connect DTC to both?
 

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