Line: 1 to 1 | ||||||||
---|---|---|---|---|---|---|---|---|
| ||||||||
Line: 8 to 8 | ||||||||
DTCDebugLog – Please log all significant test activity here | ||||||||
Added: | ||||||||
> > | ||||||||
|
Line: 1 to 1 | ||||||||
---|---|---|---|---|---|---|---|---|
| ||||||||
Line: 8 to 8 | ||||||||
DTCDebugLog – Please log all significant test activity here | ||||||||
Added: | ||||||||
> > | ||||||||
|
Line: 1 to 1 | ||||||||
---|---|---|---|---|---|---|---|---|
| ||||||||
Line: 16 to 16 | ||||||||
| ||||||||
Changed: | ||||||||
< < |
| |||||||
> > |
| |||||||
|
Line: 1 to 1 | ||||||||
---|---|---|---|---|---|---|---|---|
| ||||||||
Line: 7 to 7 | ||||||||
DTCDebugLog – Please log all significant test activity here | ||||||||
Added: | ||||||||
> > | ||||||||
|
Line: 1 to 1 | ||||||||
---|---|---|---|---|---|---|---|---|
| ||||||||
Line: 8 to 8 | ||||||||
DTCDebugLog – Please log all significant test activity here
| ||||||||
Added: | ||||||||
> > |
| |||||||
|
Line: 1 to 1 | ||||||||
---|---|---|---|---|---|---|---|---|
| ||||||||
Added: | ||||||||
> > | DTCDebugLog – Please log all significant test activity here | |||||||
|
Line: 1 to 1 | ||||||||
---|---|---|---|---|---|---|---|---|
| ||||||||
Added: | ||||||||
> > |
| |||||||
|
Line: 1 to 1 | ||||||||
---|---|---|---|---|---|---|---|---|
| ||||||||
Line: 32 to 32 | ||||||||
On the CTR2 FCLKA, TCLKA and TCLKC all enter an SN65LVDT125A LVDS crosspoint switch, and from there can be routed to the FPGA or links, possibly via an Si5319 frequency synthesizer. | ||||||||
Changed: | ||||||||
< < | Also, MiniCTR2 connects to ports 0, 1, 8 with GTX. | |||||||
> > | Also, MiniCTR2 connects to ports 0, 1, 8 with GTX. All other ports are connected to generic FPGA I/Os. | |||||||
Jeremy's requests: Transmit LHC clock on CLK1 or CLK3. TTC encoded stream on Fabric B Tx (port 2/3). TTS received on Fabric B Rx (port 2/3). | ||||||||
Changed: | ||||||||
< < | CorEdge mini crate backplane: Only CLK2, CLK3 routed. Fabric A-port 0. Fabric B-port 2. Fabrics D-G to ports 4-7. | |||||||
> > | CorEdge mini crate backplane: Only CLK2, CLK3 routed. Fabric A to port 0. Fabric B to port 2. Fabrics D-G to ports 4-7. | |||||||
Changed: | ||||||||
< < | Wu would prefer to send TTC on a fabric D-G because they are on T3. This should be OK for now but should maybe connect DTC to both? | |||||||
> > | Wu would prefer to send TTC on a fabric D-G because they are on T3. Instead I think we should send them on fabric B. | |||||||
Parts |
Line: 1 to 1 | ||||||||
---|---|---|---|---|---|---|---|---|
| ||||||||
Line: 9 to 9 | ||||||||
| ||||||||
Added: | ||||||||
> > | ||||||||
| ||||||||
Added: | ||||||||
> > |
| |||||||
Drawings | ||||||||
Line: 29 to 32 | ||||||||
On the CTR2 FCLKA, TCLKA and TCLKC all enter an SN65LVDT125A LVDS crosspoint switch, and from there can be routed to the FPGA or links, possibly via an Si5319 frequency synthesizer. | ||||||||
Changed: | ||||||||
< < | It is challenging to understand the AMC and µTCA clocking. My current understanding is that dual-star backplanes typically fanout one clock from each MCH to each AMC, and return one clock from each AMC to either MCH. | |||||||
> > | Also, MiniCTR2 connects to ports 0, 1, 8 with GTX. | |||||||
Changed: | ||||||||
< < | Wu's current thoughts: Transmit TTC clock on Fabric B (port 2/3) Tx (MCH->AMC) pair, TTC data on other pair of Fabric B. But MiniCTR2 does not connect port B to clock-friendly inputs. So, maybe back to TTC clock on CLK1, TTC data on Fabric B? | |||||||
> > | Jeremy's requests: Transmit LHC clock on CLK1 or CLK3. TTC encoded stream on Fabric B Tx (port 2/3). TTS received on Fabric B Rx (port 2/3). | |||||||
Changed: | ||||||||
< < | Also, MiniCTR2 connects to ports 0, 1, 8 with GTX. | |||||||
> > | CorEdge mini crate backplane: Only CLK2, CLK3 routed. Fabric A-port 0. Fabric B-port 2. Fabrics D-G to ports 4-7. | |||||||
Changed: | ||||||||
< < | Jeremy's requests: Transmit LHC clock on CLK1 or CLK3. TTC encoded stream on Fabric B Tx (port 3/4). TTS received on Fabric B Rx (port 3/4). | |||||||
> > | Wu would prefer to send TTC on a fabric D-G because they are on T3. This should be OK for now but should maybe connect DTC to both? | |||||||
Parts |
Line: 1 to 1 | ||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||
Line: 23 to 23 | ||||||||||||||||
| ||||||||||||||||
Changed: | ||||||||||||||||
< < |
| |||||||||||||||
> > |
| |||||||||||||||
| ||||||||||||||||
Changed: | ||||||||||||||||
< < |
| |||||||||||||||
> > |
| |||||||||||||||
On the CTR2 FCLKA, TCLKA and TCLKC all enter an SN65LVDT125A LVDS crosspoint switch, and from there can be routed to the FPGA or links, possibly via an Si5319 frequency synthesizer. | ||||||||||||||||
Line: 50 to 50 | ||||||||||||||||
| ||||||||||||||||
Deleted: | ||||||||||||||||
< < | -- EricHazen - 03 Oct 2009 | |||||||||||||||
\ No newline at end of file | ||||||||||||||||
Added: | ||||||||||||||||
> > | -- EricHazen - 22 Jan 2010 | |||||||||||||||
\ No newline at end of file |
Line: 1 to 1 | ||||||||
---|---|---|---|---|---|---|---|---|
| ||||||||
Line: 33 to 33 | ||||||||
Wu's current thoughts: Transmit TTC clock on Fabric B (port 2/3) Tx (MCH->AMC) pair, TTC data on other pair of Fabric B. But MiniCTR2 does not connect port B to clock-friendly inputs. So, maybe back to TTC clock on CLK1, TTC data on Fabric B? | ||||||||
Changed: | ||||||||
< < | Also, MiniCTR2 connects only to ports 0, 1 with GTX, so DAQ can't be on fat pipes (sigh). | |||||||
> > | Also, MiniCTR2 connects to ports 0, 1, 8 with GTX. Jeremy's requests: Transmit LHC clock on CLK1 or CLK3. TTC encoded stream on Fabric B Tx (port 3/4). TTS received on Fabric B Rx (port 3/4). | |||||||
Parts |
Line: 1 to 1 | ||||||||
---|---|---|---|---|---|---|---|---|
| ||||||||
Line: 41 to 41 | ||||||||
| ||||||||
Added: | ||||||||
> > | MicroTCA Vendors
| |||||||
-- EricHazen - 03 Oct 2009 \ No newline at end of file |
Line: 1 to 1 | ||||||||
---|---|---|---|---|---|---|---|---|
| ||||||||
Line: 29 to 29 | ||||||||
On the CTR2 FCLKA, TCLKA and TCLKC all enter an SN65LVDT125A LVDS crosspoint switch, and from there can be routed to the FPGA or links, possibly via an Si5319 frequency synthesizer. | ||||||||
Changed: | ||||||||
< < | It is challenging to understand the AMC and µTCA clocking. My current understanding is that dual-star backplanes typically fanout one clock from each MCH to each AMC, and return one clock from each AMC to either MCH. This implies to me that we should use the single clock as a fixed-frequency link clock and that the LHC clock should be embedded in the stream sent on fabric port 1 from the MCH to the AMCs. | |||||||
> > | It is challenging to understand the AMC and µTCA clocking. My current understanding is that dual-star backplanes typically fanout one clock from each MCH to each AMC, and return one clock from each AMC to either MCH. Wu's current thoughts: Transmit TTC clock on Fabric B (port 2/3) Tx (MCH->AMC) pair, TTC data on other pair of Fabric B. But MiniCTR2 does not connect port B to clock-friendly inputs. So, maybe back to TTC clock on CLK1, TTC data on Fabric B? Also, MiniCTR2 connects only to ports 0, 1 with GTX, so DAQ can't be on fat pipes (sigh). | |||||||
Parts |
Line: 1 to 1 | ||||||||
---|---|---|---|---|---|---|---|---|
| ||||||||
Line: 12 to 12 | ||||||||
| ||||||||
Added: | ||||||||
> > | Drawings
| |||||||
Design ThoughtsClocking – per AMC spec: |
Line: 1 to 1 | ||||||||
---|---|---|---|---|---|---|---|---|
| ||||||||
Line: 12 to 12 | ||||||||
| ||||||||
Changed: | ||||||||
< < | =Design Thoughts= | |||||||
> > | Design Thoughts | |||||||
Clocking – per AMC spec: | ||||||||
Line: 27 to 27 | ||||||||
It is challenging to understand the AMC and µTCA clocking. My current understanding is that dual-star backplanes typically fanout one clock from each MCH to each AMC, and return one clock from each AMC to either MCH. This implies to me that we should use the single clock as a fixed-frequency link clock and that the LHC clock should be embedded in the stream sent on fabric port 1 from the MCH to the AMCs. | ||||||||
Added: | ||||||||
> > | Parts
| |||||||
-- EricHazen - 03 Oct 2009 |
Line: 1 to 1 | |||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| |||||||||||||||||||||||||||||||
Line: 10 to 10 | |||||||||||||||||||||||||||||||
| |||||||||||||||||||||||||||||||
Added: | |||||||||||||||||||||||||||||||
> > |
| ||||||||||||||||||||||||||||||
Added: | |||||||||||||||||||||||||||||||
> > | =Design Thoughts=
Clocking – per AMC spec:
| ||||||||||||||||||||||||||||||
-- EricHazen - 03 Oct 2009 |
Line: 1 to 1 | ||||||||
---|---|---|---|---|---|---|---|---|
| ||||||||
Line: 6 to 6 | ||||||||
and fast controls and trigger feedback on port 1 of fabric A on finger 1.
| ||||||||
Changed: | ||||||||
< < | ||||||||
> > |
| |||||||
-- EricHazen - 03 Oct 2009 |
Line: 1 to 1 | ||||||||
---|---|---|---|---|---|---|---|---|
Added: | ||||||||
> > |
|