Another try. Send one event, look at LRB regs:
>lrb/stat 1
mip1_conf [40] 003e0263 [44] 00003601
Chan Empty Full Blocks Header CERR UERR IDER -WORD- -NBLK-
0 Yes No No No 0000 0000 0000 000000 000000
1 No No Yes Yes 000f 0003 0000 00018a 000001
2 No No Yes Yes 000b 0001 0000 00018a 000001
>ttc/l1a
1 L1A generated
>lrb/stat 1
mip1_conf [40] 003e0263 [44] 00003601
Chan Empty Full Blocks Header CERR UERR IDER -WORD- -NBLK-
0 Yes No No No 0000 0000 0000 000000 000000
1 No No Yes Yes 001e 0005 0000 000314 000002
2 No No Yes Yes 0018 0002 0000 000314 000002
>ttc/l1a
1 L1A generated
>lrb/stat 1
mip1_conf [40] 003e0263 [44] 00003601
Chan Empty Full Blocks Header CERR UERR IDER -WORD- -NBLK-
0 Yes No No No 0000 0000 0000 000000 000000
1 No No Yes Yes 002b 000a 0001 00049f 000003
2 No No Yes Yes 0023 0003 0000 00049e 000003
>ttc/l1a
1 L1A generated
>lrb/stat 1
mip1_conf [40] 003e0263 [44] 00003601
Chan Empty Full Blocks Header CERR UERR IDER -WORD- -NBLK-
0 Yes No No No 0000 0000 0000 000000 000000
1 No No Yes Yes 003c 000b 0001 000629 000004
2 No No Yes Yes 002c 0006 0000 000628 000004
>
The number of UERR and CERR varies widely from blcck to block.
The number of words is sometimes off by one (one extra 16-bit word). |