Difference: DCC2BoardDatabase (1 vs. 79)

Revision 7919 Jun 2013 - PhilLawson

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 72 to 72
 Errors: LRB3| 9/10/2012 | BAD LRB |
2149 BU Tested. U0 soldering problem(most likely because U10 looks OK) Multiple lines to U10 without connection   Sick
2150 904 Hospital Developed memory problems on LRB2 (spigots 6,7,8) during the Dec 2011 shutdown: http://cmsonline.cern.ch/cms-elog/750642. Repaired, test ok 2012-03-06 24 Jan 2012 OK
Changed:
<
<
2151 spare RAM replaced 2013-06-13. Tested. 6/1 OK
>
>
2151 spare RAM replaced 2013-06-13. Note: This board was removed from P5 due to OrN mismatch problems on spigot 13. Not sure if we ever tested this outside of P5: http://cmsonline.cern.ch/cms-elog/787452 6/1 OK
 
2152 FED_714 CRC Errors in Event Builder but not LRB. All errors from single LRB chip. See details below
While it would be good to run the memory test on this guy, the symptoms are not classic DRAM failure http://cmsonline.cern.ch/cms-elog/402680
31 Jan 2012: Passes LRB, DSP memory tests in 904. Good board? Worth testing at P5 		6/11/2010 Good
2153 FED_720 Developed memory problems on LRB3 (sp 9,10,11) during Dec 2011 shutdown. Removed on 24 Jan 2012 http://cmsonline.cern.ch/cms-elog/750642. Repaired, test ok 2012-03-06
8 May 2012 Installed as FED 720 at P5 		24 Jan 2012 OK
2154 FED_704 Installed on 12 Jul 2011 12 Jul 2011 OK

Revision 7812 Jun 2013 - EricHazen

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 52 to 52
 
2129 FED_730 Tested. 5/26 OK
2130 FED_727 1 July 2009: Orbit number mismatches as FED 731 (removed)
31 July 2011 Installed as FED 703
Installed as FED 727 		9/10/2012 OK
2131 FED_721 8 May 2012: Removed from FED 720 for spurious reasons (red herring): eLog entry
8 May 2012: Installed back in as FED 721 since the power cycle of previous intervention fried DRAM on 721 eLog Entry 		5/10/2012 OK
Changed:
<
<
2132 904 Hospital 23 Jan 2012: Removed because we were not receiving any events over VME in local run. Possible software issue: http://cmsonline.cern.ch/cms-elog/750159 23 Jan 2012 Sick
>
>
2132 spare RAM replaced 2013-06-13. 23 Jan 2012: Removed because we were not receiving any events over VME in local run. Possible software issue: http://cmsonline.cern.ch/cms-elog/750159 23 Jan 2012 Sick
 
2133 904 Hospital Removed due to CRC errors during intervention on other DCC issues. Suspect spurious issue: http://cmsonline.cern.ch/cms-elog/637389
31 Jan 2012: Fails LRB memory test on LRB2, LRB3. Repaired, test ok 2012-03-06 		31 Jan 2012 OK
2134 BU Returned to BU because of alleged mis-matches 5/26 Sick
2135 FED_724 Tested. HTR13 LED broken. Now fixed. 5/26 OK
2136 BU Shipped back to BU 6/9/09 per dick to CERN 5/26 OK
2137 FED_725 Tested. Initially 2 errors. 2nd time tested-no errors. Probably a wiring issue. 5/26 OK
2138 FED_726 Tested. 5/26 OK
Changed:
<
<
2139 FED_730 Installed on 3 Aug 2011 http://cmsonline.cern.ch/cms-elog/637389
Developed memory issues on LRB0 (sp 0,1,2) during Dec 2011 shutdown. Removed on 24 Jan 2012: http://cmsonline.cern.ch/cms-elog/750642
Fixed 		3 Aug 2011 OK
2140 FED_728 Tested. Initially 2 errors. 2nd time tested-no errors. Probably a wiring issue. 5/26 OK
>
>
2139 spare RAM replaced 2013-06-13. Installed on 3 Aug 2011 http://cmsonline.cern.ch/cms-elog/637389
Developed memory issues on LRB0 (sp 0,1,2) during Dec 2011 shutdown. Removed on 24 Jan 2012: http://cmsonline.cern.ch/cms-elog/750642
Fixed 		3 Aug 2011 OK
2140 spare RAM replaced 2013-06-13. Tested. Initially 2 errors. 2nd time tested-no errors. Probably a wiring issue. 5/26 OK
 
2141 FED_723 Tested. 5/26 OK
Changed:
<
<
2142 904 Hospital Prior incident as different FED (3/24/10): Was removed when we had an issue where no HTRs were sending data. No other symptoms point to DCC failure.
Removed on 10 May 2012 due to LRB DRAM failure: eLog Entry 		9/10/12 BAD LRB
>
>
2142 Spare RAM replaced 2013-06-13. Prior incident as different FED (3/24/10): Was removed when we had an issue where no HTRs were sending data. No other symptoms point to DCC failure.
Removed on 10 May 2012 due to LRB DRAM failure: eLog Entry 		9/10/12 BAD LRB
 
2143 FED_718 Tested. Ethernet error(RJ 45). Was not fixed. Returned to BU 6/9/09. Tested/shipped back to CERN
23 Jan 2012: Installed as FED 718 http://cmsonline.cern.ch/cms-elog/750159 		23 Jan 2012 OK
2144 904 Spares 16 Nov 2012: Removed due to LRB DRAM issue: eLog Entry. Not sure why we didn't address this guy over the winter
24 Oct 2012: Tested AOK after DRAM replacement eLog Entry 		10/24/12 OK
2145 FED_703 "Stops sending events down SLINK and goes to OFW at 80 kHz" . Tested OK by PDL 4/1/11 11/16 OK
Line: 72 to 72
 Errors: LRB3| 9/10/2012 | BAD LRB |
2149 BU Tested. U0 soldering problem(most likely because U10 looks OK) Multiple lines to U10 without connection   Sick
2150 904 Hospital Developed memory problems on LRB2 (spigots 6,7,8) during the Dec 2011 shutdown: http://cmsonline.cern.ch/cms-elog/750642. Repaired, test ok 2012-03-06 24 Jan 2012 OK
Changed:
<
<
2151 FED_712 Tested. 6/1 OK
>
>
2151 spare RAM replaced 2013-06-13. Tested. 6/1 OK
 
2152 FED_714 CRC Errors in Event Builder but not LRB. All errors from single LRB chip. See details below
While it would be good to run the memory test on this guy, the symptoms are not classic DRAM failure http://cmsonline.cern.ch/cms-elog/402680
31 Jan 2012: Passes LRB, DSP memory tests in 904. Good board? Worth testing at P5 		6/11/2010 Good
2153 FED_720 Developed memory problems on LRB3 (sp 9,10,11) during Dec 2011 shutdown. Removed on 24 Jan 2012 http://cmsonline.cern.ch/cms-elog/750642. Repaired, test ok 2012-03-06
8 May 2012 Installed as FED 720 at P5 		24 Jan 2012 OK
2154 FED_704 Installed on 12 Jul 2011 12 Jul 2011 OK
2155 FED_729 Installed on 3 Aug 2011 http://cmsonline.cern.ch/cms-elog/637389 3 Aug 2011 OK
2156 904 Hospital Tested. 6/1 sick? not in latest P5 scan
Changed:
<
<
2157 *CERN Tested. Warped board 6/1 OK/warped
>
>
2157 *CERN RAM replaced 2013-06-13. Tested. Warped board 6/1 OK/warped
 
2158 BU Problem: DSP FW version 0x301c reports as version 0x0 on this board. Can program manually with DCC2Tool.exe w/o issues. CRC of DSP FW reported by DCC2Tool.exe is correct. 6/1 (returned) Sick
2159 904 Hospital Tested. 8/18/11 fail LRB4 test, however, this LRB is not in use (no spigots attached to HTRs)
Developed memory issues on LRB1 (sp 3,4,5) over Dec 2011 shutdown. Removed on 24 Jan 2012: http://cmsonline.cern.ch/cms-elog/750642 Now LRB1 and LRB4 bad. Repaired, test ok 2012-03-06 		24 Jan 2012 OK
Changed:
<
<
2160 904 Spares Removed from FED 700 due to UERR on spigot 13 - 10/29/09.
27 Jan 2012: Cannot reproduce UErrs on lxcmdtest3 while running at 83 kHz. Board looks good 		27 Jan 2012 Ok
>
>
2160 904 Spares RAM replaced 2013-06-13. Removed from FED 700 due to UERR on spigot 13 - 10/29/09.
27 Jan 2012: Cannot reproduce UErrs on lxcmdtest3 while running at 83 kHz. Board looks good 		27 Jan 2012 Ok
 
2161 FED_708 Tested. 6/1 OK
Changed:
<
<
2162 FED_715 3 Aug 2011: Removed because it is not sending events over VME. Perhaps DAQ software issue? http://cmsonline.cern.ch/cms-elog/637389
26 Jan 2012: Tested on cmsmoe4 in 904. VME readout works just fine. Returning to pile of good spares 		26 Jan 2012 OK
>
>
2162 spare RAM replaced 2013-06-13. 3 Aug 2011: Removed because it is not sending events over VME. Perhaps DAQ software issue? http://cmsonline.cern.ch/cms-elog/637389
26 Jan 2012: Tested on cmsmoe4 in 904. VME readout works just fine. Returning to pile of good spares 		26 Jan 2012 OK
 
2163 BU DDR memory chip replaced 2 Aug 2011 OK
2164 FED_715 Tested. 6/9 OK
2165 FED_711 Tested. 6/9 OK
Line: 94 to 94
 
2170 BU Tested. CRC errors. Spigot zero bad?   Sick
2171 FED_717 Tested. 6/9 OK
2172 904 Hospital CRC errros on LRB FPGA serving spigots 12,13,14. Elog: http://cmsonline.cern.ch/cms-elog/605813
Replaced LRB4 @ CERN shop. All FW in FLASH except VME FW corrupted. Now fails memory test on LRB2? Elog: http://cmsonline.cern.ch/cms-elog/689158 		5 Oct 2011 Sick: bad memory
Changed:
<
<
2173 904 Hospital CRC errors from LRB FPGA serving spigots 9,10,11. Elog: http://cmsonline.cern.ch/cms-elog/753520
Failes memory test on LRB3. Repaired, test ok 2012-03-06 		24 Feb 2012 OK
>
>
2173 spare RAM replaced 2013-06-13. CRC errors from LRB FPGA serving spigots 9,10,11. Elog: http://cmsonline.cern.ch/cms-elog/753520
Failes memory test on LRB3. Repaired, test ok 2012-03-06 		24 Feb 2012 OK
 
2174 FED_702 Tested. 6/9 OK
2175 CERN Tested. Broken LED-->VME. Declared good, shipped to CERN 8/18/11 OK
2176 904 Hospital 31 July 2011: Removed from FED 703 due to BcN mismatch problems. This occurred during ramping and is likely not an actual DCC issue: http://cmsonline.cern.ch/cms-elog/631675
3 Aug 2011: Installed as FED 727 http://cmsonline.cern.ch/cms-elog/637389
2 Mar 2012: Removed due to DRAM failure (LRB2) eLog Entry 		9/10/2012 BAD LRB
Line: 117 to 117
 
2193 BU Returned ~3/10/10 w/ spigot 3 problem (CASTOR) 1/10 Sick
2194 BU Tested. 3/11/11 -- problems with spigots 3-5 (Eric/Dick) Sick
2195 FED_719 Tested. Shipped to CERN 8/18/11
Installed as FED 719 on 24 Jan 2012: http://cmsonline.cern.ch/cms-elog/750642 		8/18/11 OK
Changed:
<
<
2196 CERN Tested. Shipped to CERN 8/18/11 OK
>
>
2196 spare RAM replaced 2013-06-13. Tested. Shipped to CERN 8/18/11 OK
 
2197 BU Tested.   OK - retested@BU 11/19/12 with Charlie
2198 BU Not ever tested?   ?

Changes:

Added:
>
>		First batch of 10 boards with all RAMs replaced received back. S/N are 2142, 2140, 2139, 2160, 2157, 2162, 2173, 2196, 2132, 2151.

-- EricHazen - 12 Jun 2013

 Updated 2144 which passed tests after DRAM replacement

-- PhilLawson - 24 Oct 2012

Revision 7719 Nov 2012 - EricHazen

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 118 to 118
 
2194 BU Tested. 3/11/11 -- problems with spigots 3-5 (Eric/Dick) Sick
2195 FED_719 Tested. Shipped to CERN 8/18/11
Installed as FED 719 on 24 Jan 2012: http://cmsonline.cern.ch/cms-elog/750642 		8/18/11 OK
2196 CERN Tested. Shipped to CERN 8/18/11 OK
Changed:
<
<
2197 BU Tested.   OK
>
>
2197 BU Tested.   OK - retested@BU 11/19/12 with Charlie
 
2198 BU Not ever tested?   ?

Changes:

Revision 7624 Oct 2012 - PhilLawson

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 64 to 64
 
2141 FED_723 Tested. 5/26 OK
2142 904 Hospital Prior incident as different FED (3/24/10): Was removed when we had an issue where no HTRs were sending data. No other symptoms point to DCC failure.
Removed on 10 May 2012 due to LRB DRAM failure: eLog Entry 		9/10/12 BAD LRB
2143 FED_718 Tested. Ethernet error(RJ 45). Was not fixed. Returned to BU 6/9/09. Tested/shipped back to CERN
23 Jan 2012: Installed as FED 718 http://cmsonline.cern.ch/cms-elog/750159 		23 Jan 2012 OK
Changed:
<
<
2144 904 Hospital 16 Nov 2012: Removed due to LRB DRAM issue: eLog Entry. Not sure why we didn't address this guy over the winter 9/10/12 BAD LRB
>
>
2144 904 Spares 16 Nov 2012: Removed due to LRB DRAM issue: eLog Entry. Not sure why we didn't address this guy over the winter
24 Oct 2012: Tested AOK after DRAM replacement eLog Entry 		10/24/12 OK
 
2145 FED_703 "Stops sending events down SLINK and goes to OFW at 80 kHz" . Tested OK by PDL 4/1/11 11/16 OK
2146 BU Tested. Pin9 of HTR14 RJ45 to U14 line open. Could be a PCB problem.   Sick
2147 BU Tested. Two broken LEDs, Ethernet error(RJ 45), and CRC error. R25 cold solder,D25 is also missing. Errors fixed as of 6/3   OK
Line: 123 to 123
  Changes:
Added:
>
>		Updated 2144 which passed tests after DRAM replacement

-- PhilLawson - 24 Oct 2012

 Updated to match latest round of spares installed. List of S/N installed in P5 is correct, not sure all other information is up to date.

Revision 7520 Sep 2012 - EricHazen

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 50 to 50
 
S/N Location Notes Last update Status
2129 FED_730 Tested. 5/26 OK
Changed:
<
<
2130 P5 Spares 1 July 2009: Orbit number mismatches as FED 731 (removed)
31 July 2011 Installed as FED 703
Installed as FED 727 		9/10/2012 OK
2131 P5 Spares 8 May 2012: Removed from FED 720 for spurious reasons (red herring): eLog entry
8 May 2012: Installed back in as FED 721 since the power cycle of previous intervention fried DRAM on 721 eLog Entry 		5/10/2012 OK
>
>
2130 FED_727 1 July 2009: Orbit number mismatches as FED 731 (removed)
31 July 2011 Installed as FED 703
Installed as FED 727 		9/10/2012 OK
2131 FED_721 8 May 2012: Removed from FED 720 for spurious reasons (red herring): eLog entry
8 May 2012: Installed back in as FED 721 since the power cycle of previous intervention fried DRAM on 721 eLog Entry 		5/10/2012 OK
 
2132 904 Hospital 23 Jan 2012: Removed because we were not receiving any events over VME in local run. Possible software issue: http://cmsonline.cern.ch/cms-elog/750159 23 Jan 2012 Sick
2133 904 Hospital Removed due to CRC errors during intervention on other DCC issues. Suspect spurious issue: http://cmsonline.cern.ch/cms-elog/637389
31 Jan 2012: Fails LRB memory test on LRB2, LRB3. Repaired, test ok 2012-03-06 		31 Jan 2012 OK
2134 BU Returned to BU because of alleged mis-matches 5/26 Sick
Line: 59 to 59
 
2136 BU Shipped back to BU 6/9/09 per dick to CERN 5/26 OK
2137 FED_725 Tested. Initially 2 errors. 2nd time tested-no errors. Probably a wiring issue. 5/26 OK
2138 FED_726 Tested. 5/26 OK
Changed:
<
<
2139 904 Hospital Installed on 3 Aug 2011 http://cmsonline.cern.ch/cms-elog/637389
Developed memory issues on LRB0 (sp 0,1,2) during Dec 2011 shutdown. Removed on 24 Jan 2012: http://cmsonline.cern.ch/cms-elog/750642 		3 Aug 2011 Sick: bad memory
>
>
2139 FED_730 Installed on 3 Aug 2011 http://cmsonline.cern.ch/cms-elog/637389
Developed memory issues on LRB0 (sp 0,1,2) during Dec 2011 shutdown. Removed on 24 Jan 2012: http://cmsonline.cern.ch/cms-elog/750642
Fixed 		3 Aug 2011 OK
 
2140 FED_728 Tested. Initially 2 errors. 2nd time tested-no errors. Probably a wiring issue. 5/26 OK
2141 FED_723 Tested. 5/26 OK
2142 904 Hospital Prior incident as different FED (3/24/10): Was removed when we had an issue where no HTRs were sending data. No other symptoms point to DCC failure.
Removed on 10 May 2012 due to LRB DRAM failure: eLog Entry 		9/10/12 BAD LRB
Line: 73 to 73
 
2149 BU Tested. U0 soldering problem(most likely because U10 looks OK) Multiple lines to U10 without connection   Sick
2150 904 Hospital Developed memory problems on LRB2 (spigots 6,7,8) during the Dec 2011 shutdown: http://cmsonline.cern.ch/cms-elog/750642. Repaired, test ok 2012-03-06 24 Jan 2012 OK
2151 FED_712 Tested. 6/1 OK
Changed:
<
<
2152 904 Hospital CRC Errors in Event Builder but not LRB. All errors from single LRB chip. See details below
While it would be good to run the memory test on this guy, the symptoms are not classic DRAM failure http://cmsonline.cern.ch/cms-elog/402680
31 Jan 2012: Passes LRB, DSP memory tests in 904. Good board? Worth testing at P5 		6/11/2010 Sick
2153 FED_720l Developed memory problems on LRB3 (sp 9,10,11) during Dec 2011 shutdown. Removed on 24 Jan 2012 http://cmsonline.cern.ch/cms-elog/750642. Repaired, test ok 2012-03-06
8 May 2012 Installed as FED 720 at P5 		24 Jan 2012 OK
>
>
2152 FED_714 CRC Errors in Event Builder but not LRB. All errors from single LRB chip. See details below
While it would be good to run the memory test on this guy, the symptoms are not classic DRAM failure http://cmsonline.cern.ch/cms-elog/402680
31 Jan 2012: Passes LRB, DSP memory tests in 904. Good board? Worth testing at P5 		6/11/2010 Good
2153 FED_720 Developed memory problems on LRB3 (sp 9,10,11) during Dec 2011 shutdown. Removed on 24 Jan 2012 http://cmsonline.cern.ch/cms-elog/750642. Repaired, test ok 2012-03-06
8 May 2012 Installed as FED 720 at P5 		24 Jan 2012 OK
 
2154 FED_704 Installed on 12 Jul 2011 12 Jul 2011 OK
2155 FED_729 Installed on 3 Aug 2011 http://cmsonline.cern.ch/cms-elog/637389 3 Aug 2011 OK
Changed:
<
<
2156 FED_714 Tested. 6/1 OK
>
>
2156 904 Hospital Tested. 6/1 sick? not in latest P5 scan
 
2157 *CERN Tested. Warped board 6/1 OK/warped
2158 BU Problem: DSP FW version 0x301c reports as version 0x0 on this board. Can program manually with DCC2Tool.exe w/o issues. CRC of DSP FW reported by DCC2Tool.exe is correct. 6/1 (returned) Sick
2159 904 Hospital Tested. 8/18/11 fail LRB4 test, however, this LRB is not in use (no spigots attached to HTRs)
Developed memory issues on LRB1 (sp 3,4,5) over Dec 2011 shutdown. Removed on 24 Jan 2012: http://cmsonline.cern.ch/cms-elog/750642 Now LRB1 and LRB4 bad. Repaired, test ok 2012-03-06 		24 Jan 2012 OK
2160 904 Spares Removed from FED 700 due to UERR on spigot 13 - 10/29/09.
27 Jan 2012: Cannot reproduce UErrs on lxcmdtest3 while running at 83 kHz. Board looks good 		27 Jan 2012 Ok
2161 FED_708 Tested. 6/1 OK
Changed:
<
<
2162 904 Spares 3 Aug 2011: Removed because it is not sending events over VME. Perhaps DAQ software issue? http://cmsonline.cern.ch/cms-elog/637389
26 Jan 2012: Tested on cmsmoe4 in 904. VME readout works just fine. Returning to pile of good spares 		26 Jan 2012 OK
>
>
2162 FED_715 3 Aug 2011: Removed because it is not sending events over VME. Perhaps DAQ software issue? http://cmsonline.cern.ch/cms-elog/637389
26 Jan 2012: Tested on cmsmoe4 in 904. VME readout works just fine. Returning to pile of good spares 		26 Jan 2012 OK
 
2163 BU DDR memory chip replaced 2 Aug 2011 OK
2164 FED_715 Tested. 6/9 OK
2165 FED_711 Tested. 6/9 OK
Line: 123 to 123
  Changes:
Added:
>
>		Updated to match latest round of spares installed. List of S/N installed in P5 is correct, not sure all other information is up to date.

-- EricHazen - 20 Sep 2012

 For completeness, I would like to paste this here: 
  FED  Crate  Slot  Serial     DSP     VME     LRB0     LRB1     LRB2     LRB3     LRB4

Revision 7410 Sep 2012 - PhilLawson

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 48 to 48
 Note that you can sort the table below by clicking the column headings. Sort by Location for an easy way to check how many boards are where.
Changed:
<
<
S/N Location Notes Date shipped Status
>
>
S/N Location Notes Last update Status
 
2129 FED_730 Tested. 5/26 OK
Changed:
<
<
2130 P5 Spares 1 July 2009: Orbit number mismatches as FED 731 (removed)
31 July 2011 Installed as FED 703 		31 July 2011 OK
>
>
2130 P5 Spares 1 July 2009: Orbit number mismatches as FED 731 (removed)
31 July 2011 Installed as FED 703
Installed as FED 727 		9/10/2012 OK
 
2131 P5 Spares 8 May 2012: Removed from FED 720 for spurious reasons (red herring): eLog entry
8 May 2012: Installed back in as FED 721 since the power cycle of previous intervention fried DRAM on 721 eLog Entry 		5/10/2012 OK
2132 904 Hospital 23 Jan 2012: Removed because we were not receiving any events over VME in local run. Possible software issue: http://cmsonline.cern.ch/cms-elog/750159 23 Jan 2012 Sick
2133 904 Hospital Removed due to CRC errors during intervention on other DCC issues. Suspect spurious issue: http://cmsonline.cern.ch/cms-elog/637389
31 Jan 2012: Fails LRB memory test on LRB2, LRB3. Repaired, test ok 2012-03-06 		31 Jan 2012 OK
Line: 62 to 62
 
2139 904 Hospital Installed on 3 Aug 2011 http://cmsonline.cern.ch/cms-elog/637389
Developed memory issues on LRB0 (sp 0,1,2) during Dec 2011 shutdown. Removed on 24 Jan 2012: http://cmsonline.cern.ch/cms-elog/750642 		3 Aug 2011 Sick: bad memory
2140 FED_728 Tested. Initially 2 errors. 2nd time tested-no errors. Probably a wiring issue. 5/26 OK
2141 FED_723 Tested. 5/26 OK
Changed:
<
<
2142 904 Hospital Prior incident as different FED (3/24/10): Was removed when we had an issue where no HTRs were sending data. No other symptoms point to DCC failure.
Removed on 10 May 2012 due to LRB DRAM failure: eLog Entry 		5/10/12 BAD LRB
>
>
2142 904 Hospital Prior incident as different FED (3/24/10): Was removed when we had an issue where no HTRs were sending data. No other symptoms point to DCC failure.
Removed on 10 May 2012 due to LRB DRAM failure: eLog Entry 		9/10/12 BAD LRB
 
2143 FED_718 Tested. Ethernet error(RJ 45). Was not fixed. Returned to BU 6/9/09. Tested/shipped back to CERN
23 Jan 2012: Installed as FED 718 http://cmsonline.cern.ch/cms-elog/750159 		23 Jan 2012 OK
Changed:
<
<
2144 904 Hospital 16 Nov 2012: Removed due to LRB DRAM issue: eLog Entry. Not sure why we didn't address this guy over the winter 5/10/12 BAD LRB
>
>
2144 904 Hospital 16 Nov 2012: Removed due to LRB DRAM issue: eLog Entry. Not sure why we didn't address this guy over the winter 9/10/12 BAD LRB
 
2145 FED_703 "Stops sending events down SLINK and goes to OFW at 80 kHz" . Tested OK by PDL 4/1/11 11/16 OK
2146 BU Tested. Pin9 of HTR14 RJ45 to U14 line open. Could be a PCB problem.   Sick
2147 BU Tested. Two broken LEDs, Ethernet error(RJ 45), and CRC error. R25 cold solder,D25 is also missing. Errors fixed as of 6/3   OK
| 2148 | 904 Hospital | 8 May 2012: Failed DRAM post power cycle at P5: eLog Entry 
pseudo-random data not changing; test probably failed
Changed:
<
<		Errors: LRB3| 5/10/2012 | BAD LRB |
>
>		Errors: LRB3| 9/10/2012 | BAD LRB |
 
2149 BU Tested. U0 soldering problem(most likely because U10 looks OK) Multiple lines to U10 without connection   Sick
2150 904 Hospital Developed memory problems on LRB2 (spigots 6,7,8) during the Dec 2011 shutdown: http://cmsonline.cern.ch/cms-elog/750642. Repaired, test ok 2012-03-06 24 Jan 2012 OK
2151 FED_712 Tested. 6/1 OK
Line: 97 to 97
 
2173 904 Hospital CRC errors from LRB FPGA serving spigots 9,10,11. Elog: http://cmsonline.cern.ch/cms-elog/753520
Failes memory test on LRB3. Repaired, test ok 2012-03-06 		24 Feb 2012 OK
2174 FED_702 Tested. 6/9 OK
2175 CERN Tested. Broken LED-->VME. Declared good, shipped to CERN 8/18/11 OK
Changed:
<
<
2176 FED_727 31 July 2011: Removed from FED 703 due to BcN mismatch problems. This occurred during ramping and is likely not an actual DCC issue: http://cmsonline.cern.ch/cms-elog/631675
3 Aug 2011: Installed as FED 727 http://cmsonline.cern.ch/cms-elog/637389 		3 Aug 2011 OK
>
>
2176 904 Hospital 31 July 2011: Removed from FED 703 due to BcN mismatch problems. This occurred during ramping and is likely not an actual DCC issue: http://cmsonline.cern.ch/cms-elog/631675
3 Aug 2011: Installed as FED 727 http://cmsonline.cern.ch/cms-elog/637389
2 Mar 2012: Removed due to DRAM failure (LRB2) eLog Entry 		9/10/2012 BAD LRB
 
2177 FED_709 Tested. 7/1 OK
Changed:
<
<
2178 FED_705 Tested. Installed to replace 2160 - 10/29/09
10 May 2012: Installed as FED 705 to replace DCC with bad memoery. 		5/10/12 OK
>
>
2178 FED_705 Tested. Installed to replace 2160 - 10/29/09
10 May 2012: Installed as FED 705 to replace DCC with bad memoery. 		9/10/12 OK
 
2179 FNAL Tested. Ship to FNAL 2011-05-12 OK
2180 BU Tested. TTS link error. SLINK error.   Sick
2181 FED_700 CRC erros and "miscellaneous errors" during intervention on a different DCC problem: http://cmsonline.cern.ch/cms-elog/637389
Was eventually tested for bad memory and failed memory test. This appears to have developed memory issue during the aforementioned intervention
26 Jan 2012: This board had the affected LRB chip replaced at the CERN e-shop. Today it tested AOK at 904. Back to pile of spares 		26 Jan 2012 OK
Changed:
<
<
2182 FED_722 16 Nov 2012: Installed at P5 eLog Entry 5/10/2012 OK
>
>
2182 FED_722 16 Nov 2012: Installed at P5 eLog Entry 9/10/2012 OK
 
2183 BU Tested. Ship to MN 2011-05-12 OK
2184 BU Tested. CRC error, SLINK error. "event size of 4800 words is unreasonable"   Sick
2185 FED_713 Tested. Shipped to CERN on 8/18/11
Installed as FED 713 on 24 Jan 2012: http://cmsonline.cern.ch/cms-elog/750642 		24 Jan 2012 OK
Line: 123 to 123
  Changes:
Added:
>
>		For completeness, I would like to paste this here: 
  FED  Crate  Slot  Serial     DSP     VME     LRB0     LRB1     LRB2     LRB3     LRB4
=======================================================================================
  700      4    10    2181  0x3027   0x106    0x110    0x110    0x110    0x110    0x110
  701      4    20    2001  0x3027   0x106    0x110    0x110    0x110    0x110    0x110
  702      0    10    2174  0x3027   0x106    0x110    0x110    0x110    0x110    0x110
  703      0    20    2145  0x3027   0x106    0x110    0x110    0x110    0x110    0x110
  704      1    10    2154  0x3027   0x106    0x110    0x110    0x110    0x110    0x110
  705      1    20    2178  0x3027   0x106    0x110    0x110    0x110    0x110    0x110
  706      5    10    2169  0x3027   0x106    0x110    0x110    0x110    0x110    0x110
  707      5    20    2168  0x3027   0x106    0x110    0x110    0x110    0x110    0x110
  708     11    10    2161  0x3027   0x106    0x110    0x110    0x110    0x110    0x110
  709     11    20    2177  0x3027   0x106    0x110    0x110    0x110    0x110    0x110
  710     15    10    2186  0x3027   0x106    0x110    0x110    0x110    0x110    0x110
  711     15    20    2165  0x3027   0x106    0x110    0x110    0x110    0x110    0x110
  712     17    10    2151  0x3027   0x106    0x110    0x110    0x110    0x110    0x110
  713     17    20    2185  0x3027   0x106    0x110    0x110    0x110    0x110    0x110
  714     14    10    2156  0x3027   0x106    0x110    0x110    0x110    0x110    0x110
  715     14    20    2164  0x3027   0x106    0x110    0x110    0x110    0x110    0x110
  716     10    10    2189  0x3027   0x106    0x110    0x110    0x110    0x110    0x110
  717     10    20    2171  0x3027   0x106    0x110    0x110    0x110    0x110    0x110
  718      2    10    2143  0x3027   0x106    0x110    0x110    0x110    0x110    0x110
  719      2    20    2195  0x3027   0x106    0x110    0x110    0x110    0x110    0x110
  720      9    10    2153  0x3027   0x106    0x110    0x110    0x110    0x110    0x110
  721      9    20    2131  0x3027   0x106    0x110    0x110    0x110    0x110    0x110
  722     12    10    2182  0x3027   0x106    0x110    0x110    0x110    0x110    0x110
  723     12    20    2141  0x3027   0x106    0x110    0x110    0x110    0x110    0x110
  724      3    10    2135  0x3027   0x106    0x110    0x110    0x110    0x110    0x110
  725      3    20    2137  0x3027   0x106    0x110    0x110    0x110    0x110    0x110
  726      7    10    2138  0x3027   0x106    0x110    0x110    0x110    0x110    0x110
  727      7    20    2130  0x3027   0x106    0x110    0x110    0x110    0x110    0x110
  728      6    10    2140  0x3027   0x106    0x110    0x110    0x110    0x110    0x110
  729      6    20    2155  0x3027   0x106    0x110    0x110    0x110    0x110    0x110
  730     13    10    2129  0x3027   0x106    0x110    0x110    0x110    0x110    0x110
  731     13    20    2166  0x3027   0x106    0x110    0x110    0x110    0x110    0x110

Update to log swap of 2176 -> 2130 -- PhilLawson - 10 Sep 2012

 Update to reflect old swap of 2144->2182 -- PhilLawson - 10 Sep 2012

Revision 7310 Sep 2012 - PhilLawson

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 64 to 64
 
2141 FED_723 Tested. 5/26 OK
2142 904 Hospital Prior incident as different FED (3/24/10): Was removed when we had an issue where no HTRs were sending data. No other symptoms point to DCC failure.
Removed on 10 May 2012 due to LRB DRAM failure: eLog Entry 		5/10/12 BAD LRB
2143 FED_718 Tested. Ethernet error(RJ 45). Was not fixed. Returned to BU 6/9/09. Tested/shipped back to CERN
23 Jan 2012: Installed as FED 718 http://cmsonline.cern.ch/cms-elog/750159 		23 Jan 2012 OK
Changed:
<
<
2144 FED_722 Tested. 5/26 OK
>
>
2144 904 Hospital 16 Nov 2012: Removed due to LRB DRAM issue: eLog Entry. Not sure why we didn't address this guy over the winter 5/10/12 BAD LRB
 
2145 FED_703 "Stops sending events down SLINK and goes to OFW at 80 kHz" . Tested OK by PDL 4/1/11 11/16 OK
2146 BU Tested. Pin9 of HTR14 RJ45 to U14 line open. Could be a PCB problem.   Sick
2147 BU Tested. Two broken LEDs, Ethernet error(RJ 45), and CRC error. R25 cold solder,D25 is also missing. Errors fixed as of 6/3   OK
Line: 103 to 103
 
2179 FNAL Tested. Ship to FNAL 2011-05-12 OK
2180 BU Tested. TTS link error. SLINK error.   Sick
2181 FED_700 CRC erros and "miscellaneous errors" during intervention on a different DCC problem: http://cmsonline.cern.ch/cms-elog/637389
Was eventually tested for bad memory and failed memory test. This appears to have developed memory issue during the aforementioned intervention
26 Jan 2012: This board had the affected LRB chip replaced at the CERN e-shop. Today it tested AOK at 904. Back to pile of spares 		26 Jan 2012 OK
Changed:
<
<
2182 *CERN Tested. 7/1 OK
>
>
2182 FED_722 16 Nov 2012: Installed at P5 eLog Entry 5/10/2012 OK
 
2183 BU Tested. Ship to MN 2011-05-12 OK
2184 BU Tested. CRC error, SLINK error. "event size of 4800 words is unreasonable"   Sick
2185 FED_713 Tested. Shipped to CERN on 8/18/11
Installed as FED 713 on 24 Jan 2012: http://cmsonline.cern.ch/cms-elog/750642 		24 Jan 2012 OK
Line: 123 to 123
  Changes:
Added:
>
>		Update to reflect old swap of 2144->2182 -- PhilLawson - 10 Sep 2012
 Update to reflect swap of 2148->2131 due to memory failure on 2148 -- PhilLawson - 10 Sep 2012

Revision 7210 Sep 2012 - PhilLawson

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 51 to 51
 
S/N Location Notes Date shipped Status
2129 FED_730 Tested. 5/26 OK
2130 P5 Spares 1 July 2009: Orbit number mismatches as FED 731 (removed)
31 July 2011 Installed as FED 703 		31 July 2011 OK
Changed:
<
<
2131 P5 Spares 8 May 2012: Removed from FED 720 for spurious reasons (red herring): eLog entry 5/10/2012 OK
>
>
2131 P5 Spares 8 May 2012: Removed from FED 720 for spurious reasons (red herring): eLog entry
8 May 2012: Installed back in as FED 721 since the power cycle of previous intervention fried DRAM on 721 eLog Entry 		5/10/2012 OK
 
2132 904 Hospital 23 Jan 2012: Removed because we were not receiving any events over VME in local run. Possible software issue: http://cmsonline.cern.ch/cms-elog/750159 23 Jan 2012 Sick
2133 904 Hospital Removed due to CRC errors during intervention on other DCC issues. Suspect spurious issue: http://cmsonline.cern.ch/cms-elog/637389
31 Jan 2012: Fails LRB memory test on LRB2, LRB3. Repaired, test ok 2012-03-06 		31 Jan 2012 OK
2134 BU Returned to BU because of alleged mis-matches 5/26 Sick
Line: 68 to 68
 
2145 FED_703 "Stops sending events down SLINK and goes to OFW at 80 kHz" . Tested OK by PDL 4/1/11 11/16 OK
2146 BU Tested. Pin9 of HTR14 RJ45 to U14 line open. Could be a PCB problem.   Sick
2147 BU Tested. Two broken LEDs, Ethernet error(RJ 45), and CRC error. R25 cold solder,D25 is also missing. Errors fixed as of 6/3   OK
Changed:
<
<
2148 FED_721 Tested. 5/26 OK
>
>
2148 904 Hospital 8 May 2012: Failed DRAM post power cycle at P5: eLog Entry 
pseudo-random data not changing; test probably failed
Errors:  LRB3
 5/10/2012 BAD LRB
 
2149 BU Tested. U0 soldering problem(most likely because U10 looks OK) Multiple lines to U10 without connection   Sick
2150 904 Hospital Developed memory problems on LRB2 (spigots 6,7,8) during the Dec 2011 shutdown: http://cmsonline.cern.ch/cms-elog/750642. Repaired, test ok 2012-03-06 24 Jan 2012 OK
2151 FED_712 Tested. 6/1 OK
Line: 122 to 123
  Changes:
Added:
>
>		Update to reflect swap of 2148->2131 due to memory failure on 2148 -- PhilLawson - 10 Sep 2012
 Update to reflect unnecessary swap of 2131->2153 -- PhilLawson - 10 Sep 2012

Revision 7110 Sep 2012 - PhilLawson

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 51 to 51
 
S/N Location Notes Date shipped Status
2129 FED_730 Tested. 5/26 OK
2130 P5 Spares 1 July 2009: Orbit number mismatches as FED 731 (removed)
31 July 2011 Installed as FED 703 		31 July 2011 OK
Changed:
<
<
2131 FED_720 Tested. 5/26 OK
>
>
2131 P5 Spares 8 May 2012: Removed from FED 720 for spurious reasons (red herring): eLog entry 5/10/2012 OK
 
2132 904 Hospital 23 Jan 2012: Removed because we were not receiving any events over VME in local run. Possible software issue: http://cmsonline.cern.ch/cms-elog/750159 23 Jan 2012 Sick
2133 904 Hospital Removed due to CRC errors during intervention on other DCC issues. Suspect spurious issue: http://cmsonline.cern.ch/cms-elog/637389
31 Jan 2012: Fails LRB memory test on LRB2, LRB3. Repaired, test ok 2012-03-06 		31 Jan 2012 OK
2134 BU Returned to BU because of alleged mis-matches 5/26 Sick
Line: 73 to 73
 
2150 904 Hospital Developed memory problems on LRB2 (spigots 6,7,8) during the Dec 2011 shutdown: http://cmsonline.cern.ch/cms-elog/750642. Repaired, test ok 2012-03-06 24 Jan 2012 OK
2151 FED_712 Tested. 6/1 OK
2152 904 Hospital CRC Errors in Event Builder but not LRB. All errors from single LRB chip. See details below
While it would be good to run the memory test on this guy, the symptoms are not classic DRAM failure http://cmsonline.cern.ch/cms-elog/402680
31 Jan 2012: Passes LRB, DSP memory tests in 904. Good board? Worth testing at P5 		6/11/2010 Sick
Changed:
<
<
2153 904 Hospital Developed memory problems on LRB3 (sp 9,10,11) during Dec 2011 shutdown. Removed on 24 Jan 2012 http://cmsonline.cern.ch/cms-elog/750642. Repaired, test ok 2012-03-06 24 Jan 2012 OK
>
>
2153 FED_720l Developed memory problems on LRB3 (sp 9,10,11) during Dec 2011 shutdown. Removed on 24 Jan 2012 http://cmsonline.cern.ch/cms-elog/750642. Repaired, test ok 2012-03-06
8 May 2012 Installed as FED 720 at P5 		24 Jan 2012 OK
 
2154 FED_704 Installed on 12 Jul 2011 12 Jul 2011 OK
2155 FED_729 Installed on 3 Aug 2011 http://cmsonline.cern.ch/cms-elog/637389 3 Aug 2011 OK
2156 FED_714 Tested. 6/1 OK
Line: 122 to 122
  Changes:
Added:
>
>		Update to reflect unnecessary swap of 2131->2153 -- PhilLawson - 10 Sep 2012
 Update to reflect switch of 2178 -> 2142 on 10 May 2012 -- PhilLawson - 10 Sep 2012

Revision 7010 Sep 2012 - PhilLawson

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 98 to 98
 
2175 CERN Tested. Broken LED-->VME. Declared good, shipped to CERN 8/18/11 OK
2176 FED_727 31 July 2011: Removed from FED 703 due to BcN mismatch problems. This occurred during ramping and is likely not an actual DCC issue: http://cmsonline.cern.ch/cms-elog/631675
3 Aug 2011: Installed as FED 727 http://cmsonline.cern.ch/cms-elog/637389 		3 Aug 2011 OK
2177 FED_709 Tested. 7/1 OK
Changed:
<
<
2178 P5 Spares Tested. Installed to replace 2160 - 10/29/09 7/1 OK
>
>
2178 FED_705 Tested. Installed to replace 2160 - 10/29/09
10 May 2012: Installed as FED 705 to replace DCC with bad memoery. 		5/10/12 OK
 
2179 FNAL Tested. Ship to FNAL 2011-05-12 OK
2180 BU Tested. TTS link error. SLINK error.   Sick
2181 FED_700 CRC erros and "miscellaneous errors" during intervention on a different DCC problem: http://cmsonline.cern.ch/cms-elog/637389
Was eventually tested for bad memory and failed memory test. This appears to have developed memory issue during the aforementioned intervention
26 Jan 2012: This board had the affected LRB chip replaced at the CERN e-shop. Today it tested AOK at 904. Back to pile of spares 		26 Jan 2012 OK
Line: 122 to 122
  Changes:
Added:
>
>		Update to reflect switch of 2178 -> 2142 on 10 May 2012 -- PhilLawson - 10 Sep 2012
 SN 2173, 2159, 2133, 2153, 2150 tested after repair -- EricHazen - 06 Mar 2012

Revision 6910 Sep 2012 - PhilLawson

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 62 to 62
 
2139 904 Hospital Installed on 3 Aug 2011 http://cmsonline.cern.ch/cms-elog/637389
Developed memory issues on LRB0 (sp 0,1,2) during Dec 2011 shutdown. Removed on 24 Jan 2012: http://cmsonline.cern.ch/cms-elog/750642 		3 Aug 2011 Sick: bad memory
2140 FED_728 Tested. Initially 2 errors. 2nd time tested-no errors. Probably a wiring issue. 5/26 OK
2141 FED_723 Tested. 5/26 OK
Changed:
<
<
2142 FED_705 Prior incident as different FED (3/24/10): Was removed when we had an issue where no HTRs were sending data. No other symptoms point to DCC failure 6/11/10 OK
>
>
2142 904 Hospital Prior incident as different FED (3/24/10): Was removed when we had an issue where no HTRs were sending data. No other symptoms point to DCC failure.
Removed on 10 May 2012 due to LRB DRAM failure: eLog Entry 		5/10/12 BAD LRB
 
2143 FED_718 Tested. Ethernet error(RJ 45). Was not fixed. Returned to BU 6/9/09. Tested/shipped back to CERN
23 Jan 2012: Installed as FED 718 http://cmsonline.cern.ch/cms-elog/750159 		23 Jan 2012 OK
2144 FED_722 Tested. 5/26 OK
2145 FED_703 "Stops sending events down SLINK and goes to OFW at 80 kHz" . Tested OK by PDL 4/1/11 11/16 OK

Revision 6806 Jul 2012 - EricHazen

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.

Revision 6706 Mar 2012 - EricHazen

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 53 to 53
 
2130 P5 Spares 1 July 2009: Orbit number mismatches as FED 731 (removed)
31 July 2011 Installed as FED 703 		31 July 2011 OK
2131 FED_720 Tested. 5/26 OK
2132 904 Hospital 23 Jan 2012: Removed because we were not receiving any events over VME in local run. Possible software issue: http://cmsonline.cern.ch/cms-elog/750159 23 Jan 2012 Sick
Changed:
<
<
2133 904 Hospital Removed due to CRC errors during intervention on other DCC issues. Suspect spurious issue: http://cmsonline.cern.ch/cms-elog/637389
31 Jan 2012: Fails LRB memory test on LRB2, LRB3 		31 Jan 2012 Sick: Bad Memory
>
>
2133 904 Hospital Removed due to CRC errors during intervention on other DCC issues. Suspect spurious issue: http://cmsonline.cern.ch/cms-elog/637389
31 Jan 2012: Fails LRB memory test on LRB2, LRB3. Repaired, test ok 2012-03-06 		31 Jan 2012 OK
 
2134 BU Returned to BU because of alleged mis-matches 5/26 Sick
2135 FED_724 Tested. HTR13 LED broken. Now fixed. 5/26 OK
2136 BU Shipped back to BU 6/9/09 per dick to CERN 5/26 OK
Line: 70 to 70
 
2147 BU Tested. Two broken LEDs, Ethernet error(RJ 45), and CRC error. R25 cold solder,D25 is also missing. Errors fixed as of 6/3   OK
2148 FED_721 Tested. 5/26 OK
2149 BU Tested. U0 soldering problem(most likely because U10 looks OK) Multiple lines to U10 without connection   Sick
Changed:
<
<
2150 904 Hospital Developed memory problems on LRB2 (spigots 6,7,8) during the Dec 2011 shutdown: http://cmsonline.cern.ch/cms-elog/750642 24 Jan 2012 Sick: bad memory
>
>
2150 904 Hospital Developed memory problems on LRB2 (spigots 6,7,8) during the Dec 2011 shutdown: http://cmsonline.cern.ch/cms-elog/750642. Repaired, test ok 2012-03-06 24 Jan 2012 OK
 
2151 FED_712 Tested. 6/1 OK
2152 904 Hospital CRC Errors in Event Builder but not LRB. All errors from single LRB chip. See details below
While it would be good to run the memory test on this guy, the symptoms are not classic DRAM failure http://cmsonline.cern.ch/cms-elog/402680
31 Jan 2012: Passes LRB, DSP memory tests in 904. Good board? Worth testing at P5 		6/11/2010 Sick
Changed:
<
<
2153 904 Hospital Developed memory problems on LRB3 (sp 9,10,11) during Dec 2011 shutdown. Removed on 24 Jan 2012 http://cmsonline.cern.ch/cms-elog/750642 24 Jan 2012 Sick: bad memory
>
>
2153 904 Hospital Developed memory problems on LRB3 (sp 9,10,11) during Dec 2011 shutdown. Removed on 24 Jan 2012 http://cmsonline.cern.ch/cms-elog/750642. Repaired, test ok 2012-03-06 24 Jan 2012 OK
 
2154 FED_704 Installed on 12 Jul 2011 12 Jul 2011 OK
2155 FED_729 Installed on 3 Aug 2011 http://cmsonline.cern.ch/cms-elog/637389 3 Aug 2011 OK
2156 FED_714 Tested. 6/1 OK
2157 *CERN Tested. Warped board 6/1 OK/warped
2158 BU Problem: DSP FW version 0x301c reports as version 0x0 on this board. Can program manually with DCC2Tool.exe w/o issues. CRC of DSP FW reported by DCC2Tool.exe is correct. 6/1 (returned) Sick
Changed:
<
<
2159 904 Hospital Tested. 8/18/11 fail LRB4 test, however, this LRB is not in use (no spigots attached to HTRs)
Developed memory issues on LRB1 (sp 3,4,5) over Dec 2011 shutdown. Removed on 24 Jan 2012: http://cmsonline.cern.ch/cms-elog/750642 Now LRB1 and LRB4 bad 		24 Jan 2012 Sick: bad memory
>
>
2159 904 Hospital Tested. 8/18/11 fail LRB4 test, however, this LRB is not in use (no spigots attached to HTRs)
Developed memory issues on LRB1 (sp 3,4,5) over Dec 2011 shutdown. Removed on 24 Jan 2012: http://cmsonline.cern.ch/cms-elog/750642 Now LRB1 and LRB4 bad. Repaired, test ok 2012-03-06 		24 Jan 2012 OK
 
2160 904 Spares Removed from FED 700 due to UERR on spigot 13 - 10/29/09.
27 Jan 2012: Cannot reproduce UErrs on lxcmdtest3 while running at 83 kHz. Board looks good 		27 Jan 2012 Ok
2161 FED_708 Tested. 6/1 OK
2162 904 Spares 3 Aug 2011: Removed because it is not sending events over VME. Perhaps DAQ software issue? http://cmsonline.cern.ch/cms-elog/637389
26 Jan 2012: Tested on cmsmoe4 in 904. VME readout works just fine. Returning to pile of good spares 		26 Jan 2012 OK
Line: 93 to 93
 
2170 BU Tested. CRC errors. Spigot zero bad?   Sick
2171 FED_717 Tested. 6/9 OK
2172 904 Hospital CRC errros on LRB FPGA serving spigots 12,13,14. Elog: http://cmsonline.cern.ch/cms-elog/605813
Replaced LRB4 @ CERN shop. All FW in FLASH except VME FW corrupted. Now fails memory test on LRB2? Elog: http://cmsonline.cern.ch/cms-elog/689158 		5 Oct 2011 Sick: bad memory
Changed:
<
<
2173 904 Hospital CRC errors from LRB FPGA serving spigots 9,10,11. Elog: http://cmsonline.cern.ch/cms-elog/753520
Failes memory test on LRB3 		24 Feb 2012 OK
>
>
2173 904 Hospital CRC errors from LRB FPGA serving spigots 9,10,11. Elog: http://cmsonline.cern.ch/cms-elog/753520
Failes memory test on LRB3. Repaired, test ok 2012-03-06 		24 Feb 2012 OK
 
2174 FED_702 Tested. 6/9 OK
2175 CERN Tested. Broken LED-->VME. Declared good, shipped to CERN 8/18/11 OK
2176 FED_727 31 July 2011: Removed from FED 703 due to BcN mismatch problems. This occurred during ramping and is likely not an actual DCC issue: http://cmsonline.cern.ch/cms-elog/631675
3 Aug 2011: Installed as FED 727 http://cmsonline.cern.ch/cms-elog/637389 		3 Aug 2011 OK
Line: 122 to 122
  Changes:
Added:
>
>		SN 2173, 2159, 2133, 2153, 2150 tested after repair -- EricHazen - 06 Mar 2012
 SN 2173 fails at P5. Tested with DCC2Tool.exe and it fails LRB3. Replaced with SN 2142 as FED 705. -- PhilLawson - 24 Feb 2012

Revision 6624 Feb 2012 - PhilLawson

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 29 to 29
 

Prototype Boards

S/N Location Notes
Changed:
<
<
2001 904 Tested in MWGR 15
>
>
2001 FED_701 Tested in MWGR 15
 
2002 904  
2003 904  
2004 904  
Line: 50 to 50
 
S/N Location Notes Date shipped Status
2129 FED_730 Tested. 5/26 OK
Changed:
<
<
2130 FED_703 1 July 2009: Orbit number mismatches as FED 731 (removed)
31 July 2011 Installed as FED 703 		31 July 2011 OK
>
>
2130 P5 Spares 1 July 2009: Orbit number mismatches as FED 731 (removed)
31 July 2011 Installed as FED 703 		31 July 2011 OK
 
2131 FED_720 Tested. 5/26 OK
2132 904 Hospital 23 Jan 2012: Removed because we were not receiving any events over VME in local run. Possible software issue: http://cmsonline.cern.ch/cms-elog/750159 23 Jan 2012 Sick
2133 904 Hospital Removed due to CRC errors during intervention on other DCC issues. Suspect spurious issue: http://cmsonline.cern.ch/cms-elog/637389
31 Jan 2012: Fails LRB memory test on LRB2, LRB3 		31 Jan 2012 Sick: Bad Memory
Line: 62 to 62
 
2139 904 Hospital Installed on 3 Aug 2011 http://cmsonline.cern.ch/cms-elog/637389
Developed memory issues on LRB0 (sp 0,1,2) during Dec 2011 shutdown. Removed on 24 Jan 2012: http://cmsonline.cern.ch/cms-elog/750642 		3 Aug 2011 Sick: bad memory
2140 FED_728 Tested. Initially 2 errors. 2nd time tested-no errors. Probably a wiring issue. 5/26 OK
2141 FED_723 Tested. 5/26 OK
Changed:
<
<
2142 FED_701 Prior incident as different FED (3/24/10): Was removed when we had an issue where no HTRs were sending data. No other symptoms point to DCC failure 6/11/10 OK
>
>
2142 FED_705 Prior incident as different FED (3/24/10): Was removed when we had an issue where no HTRs were sending data. No other symptoms point to DCC failure 6/11/10 OK
 
2143 FED_718 Tested. Ethernet error(RJ 45). Was not fixed. Returned to BU 6/9/09. Tested/shipped back to CERN
23 Jan 2012: Installed as FED 718 http://cmsonline.cern.ch/cms-elog/750159 		23 Jan 2012 OK
2144 FED_722 Tested. 5/26 OK
Changed:
<
<
2145 904 Spares "Stops sending events down SLINK and goes to OFW at 80 kHz" . Tested OK by PDL 4/1/11 11/16 OK
>
>
2145 FED_703 "Stops sending events down SLINK and goes to OFW at 80 kHz" . Tested OK by PDL 4/1/11 11/16 OK
 
2146 BU Tested. Pin9 of HTR14 RJ45 to U14 line open. Could be a PCB problem.   Sick
2147 BU Tested. Two broken LEDs, Ethernet error(RJ 45), and CRC error. R25 cold solder,D25 is also missing. Errors fixed as of 6/3   OK
2148 FED_721 Tested. 5/26 OK
Line: 98 to 98
 
2175 CERN Tested. Broken LED-->VME. Declared good, shipped to CERN 8/18/11 OK
2176 FED_727 31 July 2011: Removed from FED 703 due to BcN mismatch problems. This occurred during ramping and is likely not an actual DCC issue: http://cmsonline.cern.ch/cms-elog/631675
3 Aug 2011: Installed as FED 727 http://cmsonline.cern.ch/cms-elog/637389 		3 Aug 2011 OK
2177 FED_709 Tested. 7/1 OK
Changed:
<
<
2178 FED_700 Tested. Installed to replace 2160 - 10/29/09 7/1 OK
>
>
2178 P5 Spares Tested. Installed to replace 2160 - 10/29/09 7/1 OK
 
2179 FNAL Tested. Ship to FNAL 2011-05-12 OK
2180 BU Tested. TTS link error. SLINK error.   Sick
Changed:
<
<
2181 904 Spares CRC erros and "miscellaneous errors" during intervention on a different DCC problem: http://cmsonline.cern.ch/cms-elog/637389
Was eventually tested for bad memory and failed memory test. This appears to have developed memory issue during the aforementioned intervention
26 Jan 2012: This board had the affected LRB chip replaced at the CERN e-shop. Today it tested AOK at 904. Back to pile of spares 		26 Jan 2012 OK
>
>
2181 FED_700 CRC erros and "miscellaneous errors" during intervention on a different DCC problem: http://cmsonline.cern.ch/cms-elog/637389
Was eventually tested for bad memory and failed memory test. This appears to have developed memory issue during the aforementioned intervention
26 Jan 2012: This board had the affected LRB chip replaced at the CERN e-shop. Today it tested AOK at 904. Back to pile of spares 		26 Jan 2012 OK
 
2182 *CERN Tested. 7/1 OK
2183 BU Tested. Ship to MN 2011-05-12 OK
2184 BU Tested. CRC error, SLINK error. "event size of 4800 words is unreasonable"   Sick
Line: 123 to 123
 Changes:

SN 2173 fails at P5. Tested with DCC2Tool.exe and it fails LRB3. Replaced with SN 2142 as FED 705.

Added:
>
>		-- PhilLawson - 24 Feb 2012
  SN 2133 fails memory test on LRB2, LRB3
Added:
>
>		Changes at P5: http://cmsonline.cern.ch/cms-elog/751963
 -- PhilLawson - 31 Jan 2012

SN 2145 re-checked for SLINK integrity w/ fedkit. AOK. We should install this one @ P5 to be verified with MWGR before 2012 data taking

Revision 6524 Feb 2012 - PhilLawson

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 93 to 93
 
2170 BU Tested. CRC errors. Spigot zero bad?   Sick
2171 FED_717 Tested. 6/9 OK
2172 904 Hospital CRC errros on LRB FPGA serving spigots 12,13,14. Elog: http://cmsonline.cern.ch/cms-elog/605813
Replaced LRB4 @ CERN shop. All FW in FLASH except VME FW corrupted. Now fails memory test on LRB2? Elog: http://cmsonline.cern.ch/cms-elog/689158 		5 Oct 2011 Sick: bad memory
Changed:
<
<
2173 FED_705 Tested. 6/9 OK
>
>
2173 904 Hospital CRC errors from LRB FPGA serving spigots 9,10,11. Elog: http://cmsonline.cern.ch/cms-elog/753520
Failes memory test on LRB3 		24 Feb 2012 OK
 
2174 FED_702 Tested. 6/9 OK
2175 CERN Tested. Broken LED-->VME. Declared good, shipped to CERN 8/18/11 OK
2176 FED_727 31 July 2011: Removed from FED 703 due to BcN mismatch problems. This occurred during ramping and is likely not an actual DCC issue: http://cmsonline.cern.ch/cms-elog/631675
3 Aug 2011: Installed as FED 727 http://cmsonline.cern.ch/cms-elog/637389 		3 Aug 2011 OK
Line: 122 to 122
  Changes:
Added:
>
>		SN 2173 fails at P5. Tested with DCC2Tool.exe and it fails LRB3. Replaced with SN 2142 as FED 705.
 SN 2133 fails memory test on LRB2, LRB3 -- PhilLawson - 31 Jan 2012

Revision 6431 Jan 2012 - PhilLawson

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 72 to 72
 
2149 BU Tested. U0 soldering problem(most likely because U10 looks OK) Multiple lines to U10 without connection   Sick
2150 904 Hospital Developed memory problems on LRB2 (spigots 6,7,8) during the Dec 2011 shutdown: http://cmsonline.cern.ch/cms-elog/750642 24 Jan 2012 Sick: bad memory
2151 FED_712 Tested. 6/1 OK
Changed:
<
<
2152 904 Hospital CRC Errors in Event Builder but not LRB. All errors from single LRB chip. See details below
While it would be good to run the memory test on this guy, the symptoms are not classic DRAM failure http://cmsonline.cern.ch/cms-elog/402680 		6/11/2010 Sick: bad memory
>
>
2152 904 Hospital CRC Errors in Event Builder but not LRB. All errors from single LRB chip. See details below
While it would be good to run the memory test on this guy, the symptoms are not classic DRAM failure http://cmsonline.cern.ch/cms-elog/402680
31 Jan 2012: Passes LRB, DSP memory tests in 904. Good board? Worth testing at P5 		6/11/2010 Sick
 
2153 904 Hospital Developed memory problems on LRB3 (sp 9,10,11) during Dec 2011 shutdown. Removed on 24 Jan 2012 http://cmsonline.cern.ch/cms-elog/750642 24 Jan 2012 Sick: bad memory
2154 FED_704 Installed on 12 Jul 2011 12 Jul 2011 OK
2155 FED_729 Installed on 3 Aug 2011 http://cmsonline.cern.ch/cms-elog/637389 3 Aug 2011 OK

Revision 6331 Jan 2012 - PhilLawson

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 53 to 53
 
2130 FED_703 1 July 2009: Orbit number mismatches as FED 731 (removed)
31 July 2011 Installed as FED 703 		31 July 2011 OK
2131 FED_720 Tested. 5/26 OK
2132 904 Hospital 23 Jan 2012: Removed because we were not receiving any events over VME in local run. Possible software issue: http://cmsonline.cern.ch/cms-elog/750159 23 Jan 2012 Sick
Changed:
<
<
2133 904 Hospital Removed due to CRC errors during intervention on other DCC issues. Suspect spurious issue: http://cmsonline.cern.ch/cms-elog/637389 3 Aug 2011 OK
>
>
2133 904 Hospital Removed due to CRC errors during intervention on other DCC issues. Suspect spurious issue: http://cmsonline.cern.ch/cms-elog/637389
31 Jan 2012: Fails LRB memory test on LRB2, LRB3 		31 Jan 2012 Sick: Bad Memory
 
2134 BU Returned to BU because of alleged mis-matches 5/26 Sick
2135 FED_724 Tested. HTR13 LED broken. Now fixed. 5/26 OK
2136 BU Shipped back to BU 6/9/09 per dick to CERN 5/26 OK
Line: 122 to 122
  Changes:
Added:
>
>		SN 2133 fails memory test on LRB2, LRB3 -- PhilLawson - 31 Jan 2012
 SN 2145 re-checked for SLINK integrity w/ fedkit. AOK. We should install this one @ P5 to be verified with MWGR before 2012 data taking

SN 2150 fails memory test on LRB2. This matches the symptoms of the spigots that were not working at P5.

Revision 6227 Jan 2012 - PhilLawson

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 72 to 72
 
2149 BU Tested. U0 soldering problem(most likely because U10 looks OK) Multiple lines to U10 without connection   Sick
2150 904 Hospital Developed memory problems on LRB2 (spigots 6,7,8) during the Dec 2011 shutdown: http://cmsonline.cern.ch/cms-elog/750642 24 Jan 2012 Sick: bad memory
2151 FED_712 Tested. 6/1 OK
Changed:
<
<
2152 904 Hospital CRC Errors in Event Builder but not LRB. All errors from single LRB chip. See details below
TODO: run memory test 		6/11/2010 Sick: bad memory
>
>
2152 904 Hospital CRC Errors in Event Builder but not LRB. All errors from single LRB chip. See details below
While it would be good to run the memory test on this guy, the symptoms are not classic DRAM failure http://cmsonline.cern.ch/cms-elog/402680 		6/11/2010 Sick: bad memory
 
2153 904 Hospital Developed memory problems on LRB3 (sp 9,10,11) during Dec 2011 shutdown. Removed on 24 Jan 2012 http://cmsonline.cern.ch/cms-elog/750642 24 Jan 2012 Sick: bad memory
2154 FED_704 Installed on 12 Jul 2011 12 Jul 2011 OK
2155 FED_729 Installed on 3 Aug 2011 http://cmsonline.cern.ch/cms-elog/637389 3 Aug 2011 OK

Revision 6127 Jan 2012 - PhilLawson

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 126 to 126
  SN 2150 fails memory test on LRB2. This matches the symptoms of the spigots that were not working at P5.
Changed:
<
<		SN 2160 Tests fine on lxcmdtest3 @ 43 kHz. Then we run again at 83 kHz (no TTS), HTRs are giving single bit errors which are corrected by DCC, but no UErrs show up on spigot 13 (this was the failure mode at P5). Returning to pile of good spares
>
>		SN 2160 Tests fine on lxcmdtest3 @ 43 kHz. Then we run again at 83 kHz (no TTS), HTRs are giving single bit errors which are corrected by DCC, but no UErrs show up on spigot 13 (this was the failure mode at P5). Returning to pile of good spares. Instrumented with cables to connect scope probes to monitor 3.3V and 2.5V supplies. Need to test at P5 in fully occupied crate to look for transient spikes.

SN 2132 retest VME readout. Still does not work.

  -- PhilLawson - 27 Jan 2012
Changed:
<
<		SN 2162 Tested on cmsmoe4 in 904. VME readout works just fine. Returning to pile of good spares
>
>		SN 2132 Tested on cmsmoe4 in 904. VME readout does not appear to work. xDAQ stops after 100 events (this is how many trigger credits are issued). Event Builder hyperdaq does not show any events coming in from the DCC's FED. Wu looks at register dump and states that it appears as if the VME spy buffer was already read out. Did the events get "dropped" in software? Why only for this board? Unclear. Needs further investigation.
 
Changed:
<
<		-- PhilLawson - 26 Jan 2012
>
>		SN 2162 Tested on cmsmoe4 in 904. VME readout works just fine. Returning to pile of good spares
  SN 2181 checks out AOK with xDAQ run on lxcmdtest3 post replacement of LRB1 (U11)
Deleted:
<
<		-- PhilLawson - 26 Jan 2012
 Confirmed that 2153 has bad LRB3 memory

-- PhilLawson - 26 Jan 2012

Revision 6027 Jan 2012 - PhilLawson

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 80 to 80
 
2157 *CERN Tested. Warped board 6/1 OK/warped
2158 BU Problem: DSP FW version 0x301c reports as version 0x0 on this board. Can program manually with DCC2Tool.exe w/o issues. CRC of DSP FW reported by DCC2Tool.exe is correct. 6/1 (returned) Sick
2159 904 Hospital Tested. 8/18/11 fail LRB4 test, however, this LRB is not in use (no spigots attached to HTRs)
Developed memory issues on LRB1 (sp 3,4,5) over Dec 2011 shutdown. Removed on 24 Jan 2012: http://cmsonline.cern.ch/cms-elog/750642 Now LRB1 and LRB4 bad 		24 Jan 2012 Sick: bad memory
Changed:
<
<
2160 904 Hospital Removed from FED 700 due to UERR on spigot 13 - 10/29/09. 6/1 Sick
>
>
2160 904 Spares Removed from FED 700 due to UERR on spigot 13 - 10/29/09.
27 Jan 2012: Cannot reproduce UErrs on lxcmdtest3 while running at 83 kHz. Board looks good 		27 Jan 2012 Ok
 
2161 FED_708 Tested. 6/1 OK
2162 904 Spares 3 Aug 2011: Removed because it is not sending events over VME. Perhaps DAQ software issue? http://cmsonline.cern.ch/cms-elog/637389
26 Jan 2012: Tested on cmsmoe4 in 904. VME readout works just fine. Returning to pile of good spares 		26 Jan 2012 OK
2163 BU DDR memory chip replaced 2 Aug 2011 OK
Line: 122 to 122
  Changes:
Added:
>
>		SN 2145 re-checked for SLINK integrity w/ fedkit. AOK. We should install this one @ P5 to be verified with MWGR before 2012 data taking

SN 2150 fails memory test on LRB2. This matches the symptoms of the spigots that were not working at P5.

SN 2160 Tests fine on lxcmdtest3 @ 43 kHz. Then we run again at 83 kHz (no TTS), HTRs are giving single bit errors which are corrected by DCC, but no UErrs show up on spigot 13 (this was the failure mode at P5). Returning to pile of good spares

-- PhilLawson - 27 Jan 2012

 SN 2162 Tested on cmsmoe4 in 904. VME readout works just fine. Returning to pile of good spares

-- PhilLawson - 26 Jan 2012

Revision 5926 Jan 2012 - PhilLawson

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 82 to 82
 
2159 904 Hospital Tested. 8/18/11 fail LRB4 test, however, this LRB is not in use (no spigots attached to HTRs)
Developed memory issues on LRB1 (sp 3,4,5) over Dec 2011 shutdown. Removed on 24 Jan 2012: http://cmsonline.cern.ch/cms-elog/750642 Now LRB1 and LRB4 bad 		24 Jan 2012 Sick: bad memory
2160 904 Hospital Removed from FED 700 due to UERR on spigot 13 - 10/29/09. 6/1 Sick
2161 FED_708 Tested. 6/1 OK
Changed:
<
<
2162 904 Hospital 3 Aug 2011: Removed because it is not sending events over VME. Perhaps DAQ software issue? http://cmsonline.cern.ch/cms-elog/637389 6/1 OK
>
>
2162 904 Spares 3 Aug 2011: Removed because it is not sending events over VME. Perhaps DAQ software issue? http://cmsonline.cern.ch/cms-elog/637389
26 Jan 2012: Tested on cmsmoe4 in 904. VME readout works just fine. Returning to pile of good spares 		26 Jan 2012 OK
 
2163 BU DDR memory chip replaced 2 Aug 2011 OK
2164 FED_715 Tested. 6/9 OK
2165 FED_711 Tested. 6/9 OK
Line: 122 to 122
  Changes:
Added:
>
>		SN 2162 Tested on cmsmoe4 in 904. VME readout works just fine. Returning to pile of good spares

-- PhilLawson - 26 Jan 2012

 SN 2181 checks out AOK with xDAQ run on lxcmdtest3 post replacement of LRB1 (U11)

-- PhilLawson - 26 Jan 2012

Revision 5826 Jan 2012 - PhilLawson

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 122 to 122
  Changes:
Added:
>
>		SN 2181 checks out AOK with xDAQ run on lxcmdtest3 post replacement of LRB1 (U11)

-- PhilLawson - 26 Jan 2012

 Confirmed that 2153 has bad LRB3 memory

-- PhilLawson - 26 Jan 2012

Revision 5726 Jan 2012 - PhilLawson

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 101 to 101
 
2178 FED_700 Tested. Installed to replace 2160 - 10/29/09 7/1 OK
2179 FNAL Tested. Ship to FNAL 2011-05-12 OK
2180 BU Tested. TTS link error. SLINK error.   Sick
Changed:
<
<
2181 904 Hospital CRC erros and "miscellaneous errors" during intervention on a different DCC problem: http://cmsonline.cern.ch/cms-elog/637389
Was eventually tested for bad memory and failed memory test. This appears to have developed memory issue during the aforementioned intervention 		3 Aug 2011 Sick: bad memory
>
>
2181 904 Spares CRC erros and "miscellaneous errors" during intervention on a different DCC problem: http://cmsonline.cern.ch/cms-elog/637389
Was eventually tested for bad memory and failed memory test. This appears to have developed memory issue during the aforementioned intervention
26 Jan 2012: This board had the affected LRB chip replaced at the CERN e-shop. Today it tested AOK at 904. Back to pile of spares 		26 Jan 2012 OK
 
2182 *CERN Tested. 7/1 OK
2183 BU Tested. Ship to MN 2011-05-12 OK
2184 BU Tested. CRC error, SLINK error. "event size of 4800 words is unreasonable"   Sick

Revision 5626 Jan 2012 - PhilLawson

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 73 to 73
 
2150 904 Hospital Developed memory problems on LRB2 (spigots 6,7,8) during the Dec 2011 shutdown: http://cmsonline.cern.ch/cms-elog/750642 24 Jan 2012 Sick: bad memory
2151 FED_712 Tested. 6/1 OK
2152 904 Hospital CRC Errors in Event Builder but not LRB. All errors from single LRB chip. See details below
TODO: run memory test 		6/11/2010 Sick: bad memory
Changed:
<
<
2153 904 Hospital Developed memory problems on LRB4 (sp 9,10,11) during Dec 2011 shutdown. Removed on 24 Jan 2012 http://cmsonline.cern.ch/cms-elog/750642
Phil's notes show LRB0 as bad. RE-TEST THIS ONE 		24 Jan 2012 Sick: bad memory
>
>
2153 904 Hospital Developed memory problems on LRB3 (sp 9,10,11) during Dec 2011 shutdown. Removed on 24 Jan 2012 http://cmsonline.cern.ch/cms-elog/750642 24 Jan 2012 Sick: bad memory
 
2154 FED_704 Installed on 12 Jul 2011 12 Jul 2011 OK
2155 FED_729 Installed on 3 Aug 2011 http://cmsonline.cern.ch/cms-elog/637389 3 Aug 2011 OK
2156 FED_714 Tested. 6/1 OK
Line: 122 to 122
  Changes:
Added:
>
>		Confirmed that 2153 has bad LRB3 memory

-- PhilLawson - 26 Jan 2012

 Much eLog sifting to bring list up to date:

-- PhilLawson - 25 Jan 2012

Revision 5525 Jan 2012 - PhilLawson

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 101 to 101
 
2178 FED_700 Tested. Installed to replace 2160 - 10/29/09 7/1 OK
2179 FNAL Tested. Ship to FNAL 2011-05-12 OK
2180 BU Tested. TTS link error. SLINK error.   Sick
Changed:
<
<
2181 904 Hospital CRC erros and "miscellaneous errors" during intervention on a different DCC problem: http://cmsonline.cern.ch/cms-elog/637389 3 Aug 2011 Sick
>
>
2181 904 Hospital CRC erros and "miscellaneous errors" during intervention on a different DCC problem: http://cmsonline.cern.ch/cms-elog/637389
Was eventually tested for bad memory and failed memory test. This appears to have developed memory issue during the aforementioned intervention 		3 Aug 2011 Sick: bad memory
 
2182 *CERN Tested. 7/1 OK
2183 BU Tested. Ship to MN 2011-05-12 OK
2184 BU Tested. CRC error, SLINK error. "event size of 4800 words is unreasonable"   Sick

Revision 5425 Jan 2012 - PhilLawson

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 92 to 92
 
2169 FED_706 Tested. 6/9 OK
2170 BU Tested. CRC errors. Spigot zero bad?   Sick
2171 FED_717 Tested. 6/9 OK
Changed:
<
<
2172 904 Hospital CRC errros on LRB FPGA serving spigots 12,13,14. Elog: http://cmsonline.cern.ch/cms-elog/605813
Replaced LRB4 @ CERN shop. All FW in FLASH except VME FW corrupted. Now fails memory test on LRB2? Elog: http://cmsonline.cern.ch/cms-elog/689158 		5 Oct 2011 Sick
>
>
2172 904 Hospital CRC errros on LRB FPGA serving spigots 12,13,14. Elog: http://cmsonline.cern.ch/cms-elog/605813
Replaced LRB4 @ CERN shop. All FW in FLASH except VME FW corrupted. Now fails memory test on LRB2? Elog: http://cmsonline.cern.ch/cms-elog/689158 		5 Oct 2011 Sick: bad memory
 
2173 FED_705 Tested. 6/9 OK
2174 FED_702 Tested. 6/9 OK
2175 CERN Tested. Broken LED-->VME. Declared good, shipped to CERN 8/18/11 OK

Revision 5325 Jan 2012 - PhilLawson

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 72 to 72
 
2149 BU Tested. U0 soldering problem(most likely because U10 looks OK) Multiple lines to U10 without connection   Sick
2150 904 Hospital Developed memory problems on LRB2 (spigots 6,7,8) during the Dec 2011 shutdown: http://cmsonline.cern.ch/cms-elog/750642 24 Jan 2012 Sick: bad memory
2151 FED_712 Tested. 6/1 OK
Changed:
<
<
2152 904 Hospital CRC Errors in Event Builder but not LRB. All errors from single LRB chip. See details below 6/11/2010 Sick
>
>
2152 904 Hospital CRC Errors in Event Builder but not LRB. All errors from single LRB chip. See details below
TODO: run memory test 		6/11/2010 Sick: bad memory
 
2153 904 Hospital Developed memory problems on LRB4 (sp 9,10,11) during Dec 2011 shutdown. Removed on 24 Jan 2012 http://cmsonline.cern.ch/cms-elog/750642
Phil's notes show LRB0 as bad. RE-TEST THIS ONE 		24 Jan 2012 Sick: bad memory
2154 FED_704 Installed on 12 Jul 2011 12 Jul 2011 OK
2155 FED_729 Installed on 3 Aug 2011 http://cmsonline.cern.ch/cms-elog/637389 3 Aug 2011 OK
2156 FED_714 Tested. 6/1 OK
2157 *CERN Tested. Warped board 6/1 OK/warped
2158 BU Problem: DSP FW version 0x301c reports as version 0x0 on this board. Can program manually with DCC2Tool.exe w/o issues. CRC of DSP FW reported by DCC2Tool.exe is correct. 6/1 (returned) Sick
Changed:
<
<
2159 FED_713 Tested. 8/18/11 fail LRB4 test, however, this LRB is not in use (no spigots attached to HTRs)
Developed memory issues on LRB1 (sp 3,4,5) over Dec 2011 shutdown. Removed on 24 Jan 2012: http://cmsonline.cern.ch/cms-elog/750642 Now LRB1 and LRB4 bad 		24 Jan 2012 Sick: bad memory
>
>
2159 904 Hospital Tested. 8/18/11 fail LRB4 test, however, this LRB is not in use (no spigots attached to HTRs)
Developed memory issues on LRB1 (sp 3,4,5) over Dec 2011 shutdown. Removed on 24 Jan 2012: http://cmsonline.cern.ch/cms-elog/750642 Now LRB1 and LRB4 bad 		24 Jan 2012 Sick: bad memory
 
2160 904 Hospital Removed from FED 700 due to UERR on spigot 13 - 10/29/09. 6/1 Sick
2161 FED_708 Tested. 6/1 OK
2162 904 Hospital 3 Aug 2011: Removed because it is not sending events over VME. Perhaps DAQ software issue? http://cmsonline.cern.ch/cms-elog/637389 6/1 OK

Revision 5225 Jan 2012 - PhilLawson

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 122 to 122
  Changes:
Added:
>
>		Much eLog sifting to bring list up to date:

-- PhilLawson - 25 Jan 2012

 S/N 2159 fails LRB4 link/memory test in the pit as FED 713. PDL discovered that these spigots are not in use on this FED and opted not to swap out.

-- EricHazen - 18 Aug 2011

Revision 5125 Jan 2012 - PhilLawson

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 52 to 52
 
2129 FED_730 Tested. 5/26 OK
2130 FED_703 1 July 2009: Orbit number mismatches as FED 731 (removed)
31 July 2011 Installed as FED 703 		31 July 2011 OK
2131 FED_720 Tested. 5/26 OK
Changed:
<
<
2132 FED_718 Tested. 5/26 OK
>
>
2132 904 Hospital 23 Jan 2012: Removed because we were not receiving any events over VME in local run. Possible software issue: http://cmsonline.cern.ch/cms-elog/750159 23 Jan 2012 Sick
 
2133 904 Hospital Removed due to CRC errors during intervention on other DCC issues. Suspect spurious issue: http://cmsonline.cern.ch/cms-elog/637389 3 Aug 2011 OK
2134 BU Returned to BU because of alleged mis-matches 5/26 Sick
2135 FED_724 Tested. HTR13 LED broken. Now fixed. 5/26 OK
Line: 63 to 63
 
2140 FED_728 Tested. Initially 2 errors. 2nd time tested-no errors. Probably a wiring issue. 5/26 OK
2141 FED_723 Tested. 5/26 OK
2142 FED_701 Prior incident as different FED (3/24/10): Was removed when we had an issue where no HTRs were sending data. No other symptoms point to DCC failure 6/11/10 OK
Changed:
<
<
2143 CERN Tested. Ethernet error(RJ 45). Was not fixed. Returned to BU 6/9/09. Tested/shipped back to CERN 8/18/11 OK
>
>
2143 FED_718 Tested. Ethernet error(RJ 45). Was not fixed. Returned to BU 6/9/09. Tested/shipped back to CERN
23 Jan 2012: Installed as FED 718 http://cmsonline.cern.ch/cms-elog/750159 		23 Jan 2012 OK
 
2144 FED_722 Tested. 5/26 OK
2145 904 Spares "Stops sending events down SLINK and goes to OFW at 80 kHz" . Tested OK by PDL 4/1/11 11/16 OK
2146 BU Tested. Pin9 of HTR14 RJ45 to U14 line open. Could be a PCB problem.   Sick

Revision 5025 Jan 2012 - PhilLawson

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 79 to 79
 
2156 FED_714 Tested. 6/1 OK
2157 *CERN Tested. Warped board 6/1 OK/warped
2158 BU Problem: DSP FW version 0x301c reports as version 0x0 on this board. Can program manually with DCC2Tool.exe w/o issues. CRC of DSP FW reported by DCC2Tool.exe is correct. 6/1 (returned) Sick
Changed:
<
<
2159 FED_713 Tested. 8/18/11 fail LRB4 test, however, this LRB is not in use (no spigots attached to HTRs) 6/1 LRB4 sick
>
>
2159 FED_713 Tested. 8/18/11 fail LRB4 test, however, this LRB is not in use (no spigots attached to HTRs)
Developed memory issues on LRB1 (sp 3,4,5) over Dec 2011 shutdown. Removed on 24 Jan 2012: http://cmsonline.cern.ch/cms-elog/750642 Now LRB1 and LRB4 bad 		24 Jan 2012 Sick: bad memory
 
2160 904 Hospital Removed from FED 700 due to UERR on spigot 13 - 10/29/09. 6/1 Sick
2161 FED_708 Tested. 6/1 OK
2162 904 Hospital 3 Aug 2011: Removed because it is not sending events over VME. Perhaps DAQ software issue? http://cmsonline.cern.ch/cms-elog/637389 6/1 OK
Line: 105 to 105
 
2182 *CERN Tested. 7/1 OK
2183 BU Tested. Ship to MN 2011-05-12 OK
2184 BU Tested. CRC error, SLINK error. "event size of 4800 words is unreasonable"   Sick
Changed:
<
<
2185 CERN Tested. Shipped to CERN 8/18/11 OK
>
>
2185 FED_713 Tested. Shipped to CERN on 8/18/11
Installed as FED 713 on 24 Jan 2012: http://cmsonline.cern.ch/cms-elog/750642 		24 Jan 2012 OK
 
2186 FED_710 Tested. Shipped to CERN on 8/18/11
Installed as FED 710 on 24 Jan 2012: http://cmsonline.cern.ch/cms-elog/750642 		24 Jan 2012 OK
2187 BU Board is warped. won't fit into crate.   Sick
2188 BU Tested. Ethernet RJ45 error.   Sick
Changed:
<
<
2189 CERN Tested. Shipped to CERN on 8/18/11
Installed as FED 716 on 24 Jan 2012 http://cmsonline.cern.ch/cms-elog/750642 		24 Jan 2012 OK
>
>
2189 FED_716 Tested. Shipped to CERN on 8/18/11
Installed as FED 716 on 24 Jan 2012 http://cmsonline.cern.ch/cms-elog/750642 		24 Jan 2012 OK
 
2190 CERN Tested. 1/10 OK
2191 CERN Tested. 1/10 OK
2192 CERN Tested. 1/10 OK

Revision 4925 Jan 2012 - PhilLawson

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 73 to 73
 
2150 904 Hospital Developed memory problems on LRB2 (spigots 6,7,8) during the Dec 2011 shutdown: http://cmsonline.cern.ch/cms-elog/750642 24 Jan 2012 Sick: bad memory
2151 FED_712 Tested. 6/1 OK
2152 904 Hospital CRC Errors in Event Builder but not LRB. All errors from single LRB chip. See details below 6/11/2010 Sick
Changed:
<
<
2153 FED_710 Tested. 6/1 OK
>
>
2153 904 Hospital Developed memory problems on LRB4 (sp 9,10,11) during Dec 2011 shutdown. Removed on 24 Jan 2012 http://cmsonline.cern.ch/cms-elog/750642
Phil's notes show LRB0 as bad. RE-TEST THIS ONE 		24 Jan 2012 Sick: bad memory
 
2154 FED_704 Installed on 12 Jul 2011 12 Jul 2011 OK
2155 FED_729 Installed on 3 Aug 2011 http://cmsonline.cern.ch/cms-elog/637389 3 Aug 2011 OK
2156 FED_714 Tested. 6/1 OK
Line: 106 to 106
 
2183 BU Tested. Ship to MN 2011-05-12 OK
2184 BU Tested. CRC error, SLINK error. "event size of 4800 words is unreasonable"   Sick
2185 CERN Tested. Shipped to CERN 8/18/11 OK
Changed:
<
<
2186 CERN Tested. Shipped to CERN 8/18/11 OK
>
>
2186 FED_710 Tested. Shipped to CERN on 8/18/11
Installed as FED 710 on 24 Jan 2012: http://cmsonline.cern.ch/cms-elog/750642 		24 Jan 2012 OK
 
2187 BU Board is warped. won't fit into crate.   Sick
2188 BU Tested. Ethernet RJ45 error.   Sick
2189 CERN Tested. Shipped to CERN on 8/18/11
Installed as FED 716 on 24 Jan 2012 http://cmsonline.cern.ch/cms-elog/750642 		24 Jan 2012 OK

Revision 4825 Jan 2012 - PhilLawson

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 59 to 59
 
2136 BU Shipped back to BU 6/9/09 per dick to CERN 5/26 OK
2137 FED_725 Tested. Initially 2 errors. 2nd time tested-no errors. Probably a wiring issue. 5/26 OK
2138 FED_726 Tested. 5/26 OK
Changed:
<
<
2139 FED_716 Installed on 3 Aug 2011 http://cmsonline.cern.ch/cms-elog/637389 3 Aug 2011 OK
>
>
2139 904 Hospital Installed on 3 Aug 2011 http://cmsonline.cern.ch/cms-elog/637389
Developed memory issues on LRB0 (sp 0,1,2) during Dec 2011 shutdown. Removed on 24 Jan 2012: http://cmsonline.cern.ch/cms-elog/750642 		3 Aug 2011 Sick: bad memory
 
2140 FED_728 Tested. Initially 2 errors. 2nd time tested-no errors. Probably a wiring issue. 5/26 OK
2141 FED_723 Tested. 5/26 OK
2142 FED_701 Prior incident as different FED (3/24/10): Was removed when we had an issue where no HTRs were sending data. No other symptoms point to DCC failure 6/11/10 OK
Line: 109 to 109
 
2186 CERN Tested. Shipped to CERN 8/18/11 OK
2187 BU Board is warped. won't fit into crate.   Sick
2188 BU Tested. Ethernet RJ45 error.   Sick
Changed:
<
<
2189 CERN Tested. Shipped to CERN 8/18/11 OK
>
>
2189 CERN Tested. Shipped to CERN on 8/18/11
Installed as FED 716 on 24 Jan 2012 http://cmsonline.cern.ch/cms-elog/750642 		24 Jan 2012 OK
 
2190 CERN Tested. 1/10 OK
2191 CERN Tested. 1/10 OK
2192 CERN Tested. 1/10 OK

Revision 4725 Jan 2012 - PhilLawson

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 70 to 70
 
2147 BU Tested. Two broken LEDs, Ethernet error(RJ 45), and CRC error. R25 cold solder,D25 is also missing. Errors fixed as of 6/3   OK
2148 FED_721 Tested. 5/26 OK
2149 BU Tested. U0 soldering problem(most likely because U10 looks OK) Multiple lines to U10 without connection   Sick
Changed:
<
<
2150 FED_719 Tested. 7/1 OK
>
>
2150 904 Hospital Developed memory problems on LRB2 (spigots 6,7,8) during the Dec 2011 shutdown: http://cmsonline.cern.ch/cms-elog/750642 24 Jan 2012 Sick: bad memory
 
2151 FED_712 Tested. 6/1 OK
2152 904 Hospital CRC Errors in Event Builder but not LRB. All errors from single LRB chip. See details below 6/11/2010 Sick
2153 FED_710 Tested. 6/1 OK
Line: 115 to 115
 
2192 CERN Tested. 1/10 OK
2193 BU Returned ~3/10/10 w/ spigot 3 problem (CASTOR) 1/10 Sick
2194 BU Tested. 3/11/11 -- problems with spigots 3-5 (Eric/Dick) Sick
Changed:
<
<
2195 CERN Tested. Shipped to CERN 8/18/11 OK
>
>
2195 FED_719 Tested. Shipped to CERN 8/18/11
Installed as FED 719 on 24 Jan 2012: http://cmsonline.cern.ch/cms-elog/750642 		8/18/11 OK
 
2196 CERN Tested. Shipped to CERN 8/18/11 OK
2197 BU Tested.   OK
2198 BU Not ever tested?   ?

Revision 4625 Jan 2012 - PhilLawson

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 50 to 50
 
S/N Location Notes Date shipped Status
2129 FED_730 Tested. 5/26 OK
Changed:
<
<
2130 *904 Hospital Orbit number mismatches as FED 731 01-jul-2009 (removed) 5/26 Sick
>
>
2130 FED_703 1 July 2009: Orbit number mismatches as FED 731 (removed)
31 July 2011 Installed as FED 703 		31 July 2011 OK
 
2131 FED_720 Tested. 5/26 OK
2132 FED_718 Tested. 5/26 OK
2133 904 Hospital Removed due to CRC errors during intervention on other DCC issues. Suspect spurious issue: http://cmsonline.cern.ch/cms-elog/637389 3 Aug 2011 OK

Revision 4525 Jan 2012 - PhilLawson

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 82 to 82
 
2159 FED_713 Tested. 8/18/11 fail LRB4 test, however, this LRB is not in use (no spigots attached to HTRs) 6/1 LRB4 sick
2160 904 Hospital Removed from FED 700 due to UERR on spigot 13 - 10/29/09. 6/1 Sick
2161 FED_708 Tested. 6/1 OK
Changed:
<
<
2162 FED_716 Tested. 6/1 OK
>
>
2162 904 Hospital 3 Aug 2011: Removed because it is not sending events over VME. Perhaps DAQ software issue? http://cmsonline.cern.ch/cms-elog/637389 6/1 OK
 
2163 BU DDR memory chip replaced 2 Aug 2011 OK
2164 FED_715 Tested. 6/9 OK
2165 FED_711 Tested. 6/9 OK

Revision 4425 Jan 2012 - PhilLawson

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 59 to 59
 
2136 BU Shipped back to BU 6/9/09 per dick to CERN 5/26 OK
2137 FED_725 Tested. Initially 2 errors. 2nd time tested-no errors. Probably a wiring issue. 5/26 OK
2138 FED_726 Tested. 5/26 OK
Changed:
<
<
2139 *CERN Tested. 5/26 OK
>
>
2139 FED_716 Installed on 3 Aug 2011 http://cmsonline.cern.ch/cms-elog/637389 3 Aug 2011 OK
 
2140 FED_728 Tested. Initially 2 errors. 2nd time tested-no errors. Probably a wiring issue. 5/26 OK
2141 FED_723 Tested. 5/26 OK
2142 FED_701 Prior incident as different FED (3/24/10): Was removed when we had an issue where no HTRs were sending data. No other symptoms point to DCC failure 6/11/10 OK

Revision 4325 Jan 2012 - PhilLawson

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 53 to 53
 
2130 *904 Hospital Orbit number mismatches as FED 731 01-jul-2009 (removed) 5/26 Sick
2131 FED_720 Tested. 5/26 OK
2132 FED_718 Tested. 5/26 OK
Changed:
<
<
2133 FED_729 Tested. 5/26 OK
>
>
2133 904 Hospital Removed due to CRC errors during intervention on other DCC issues. Suspect spurious issue: http://cmsonline.cern.ch/cms-elog/637389 3 Aug 2011 OK
 
2134 BU Returned to BU because of alleged mis-matches 5/26 Sick
2135 FED_724 Tested. HTR13 LED broken. Now fixed. 5/26 OK
2136 BU Shipped back to BU 6/9/09 per dick to CERN 5/26 OK
Line: 75 to 75
 
2152 904 Hospital CRC Errors in Event Builder but not LRB. All errors from single LRB chip. See details below 6/11/2010 Sick
2153 FED_710 Tested. 6/1 OK
2154 FED_704 Installed on 12 Jul 2011 12 Jul 2011 OK
Changed:
<
<
2155 *CERN Tested. 6/1 OK
>
>
2155 FED_729 Installed on 3 Aug 2011 http://cmsonline.cern.ch/cms-elog/637389 3 Aug 2011 OK
 
2156 FED_714 Tested. 6/1 OK
2157 *CERN Tested. Warped board 6/1 OK/warped
2158 BU Problem: DSP FW version 0x301c reports as version 0x0 on this board. Can program manually with DCC2Tool.exe w/o issues. CRC of DSP FW reported by DCC2Tool.exe is correct. 6/1 (returned) Sick

Revision 4225 Jan 2012 - PhilLawson

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 96 to 96
 
2173 FED_705 Tested. 6/9 OK
2174 FED_702 Tested. 6/9 OK
2175 CERN Tested. Broken LED-->VME. Declared good, shipped to CERN 8/18/11 OK
Changed:
<
<
2176 FED_703 Tested. 6/9 OK
>
>
2176 FED_727 31 July 2011: Removed from FED 703 due to BcN mismatch problems. This occurred during ramping and is likely not an actual DCC issue: http://cmsonline.cern.ch/cms-elog/631675
3 Aug 2011: Installed as FED 727 http://cmsonline.cern.ch/cms-elog/637389 		3 Aug 2011 OK
 
2177 FED_709 Tested. 7/1 OK
2178 FED_700 Tested. Installed to replace 2160 - 10/29/09 7/1 OK
2179 FNAL Tested. Ship to FNAL 2011-05-12 OK
2180 BU Tested. TTS link error. SLINK error.   Sick
Changed:
<
<
2181 FED_727 Tested. 4/13/10 OK
>
>
2181 904 Hospital CRC erros and "miscellaneous errors" during intervention on a different DCC problem: http://cmsonline.cern.ch/cms-elog/637389 3 Aug 2011 Sick
 
2182 *CERN Tested. 7/1 OK
2183 BU Tested. Ship to MN 2011-05-12 OK
2184 BU Tested. CRC error, SLINK error. "event size of 4800 words is unreasonable"   Sick

Revision 4125 Jan 2012 - PhilLawson

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 92 to 92
 
2169 FED_706 Tested. 6/9 OK
2170 BU Tested. CRC errors. Spigot zero bad?   Sick
2171 FED_717 Tested. 6/9 OK
Changed:
<
<
2172 904 Hospital CRC errros on LRB FPGA serving spigots 12,13,14. Elog: http://cmsonline.cern.ch/cms-elog/605813 12 Jul 2011 Sick
>
>
2172 904 Hospital CRC errros on LRB FPGA serving spigots 12,13,14. Elog: http://cmsonline.cern.ch/cms-elog/605813
Replaced LRB4 @ CERN shop. All FW in FLASH except VME FW corrupted. Now fails memory test on LRB2? Elog: http://cmsonline.cern.ch/cms-elog/689158 		5 Oct 2011 Sick
 
2173 FED_705 Tested. 6/9 OK
2174 FED_702 Tested. 6/9 OK
2175 CERN Tested. Broken LED-->VME. Declared good, shipped to CERN 8/18/11 OK

Revision 4024 Jan 2012 - PhilLawson

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 71 to 71
 
2148 FED_721 Tested. 5/26 OK
2149 BU Tested. U0 soldering problem(most likely because U10 looks OK) Multiple lines to U10 without connection   Sick
2150 FED_719 Tested. 7/1 OK
Added:
>
>
2151 FED_712 Tested. 6/1 OK
 
2152 904 Hospital CRC Errors in Event Builder but not LRB. All errors from single LRB chip. See details below 6/11/2010 Sick
2153 FED_710 Tested. 6/1 OK
2154 FED_704 Installed on 12 Jul 2011 12 Jul 2011 OK
Line: 147 to 148
 Readout 10E6 events at this rate with no SLINK errors. Good enough for me.
Added:
>
>		-- PhilLawson - 24 Jan 2012
  • Replaced line for 2151. This was accidentally removed during an edit a long while back. Good thing for twiki history!
 -- EricHazen - 01 Apr 2011

  • SN 2163 showed CRC errors on LRB chip serving spigots 0,1,2

Revision 3924 Jan 2012 - PhilLawson

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 72 to 72
 
2149 BU Tested. U0 soldering problem(most likely because U10 looks OK) Multiple lines to U10 without connection   Sick
2150 FED_719 Tested. 7/1 OK
2152 904 Hospital CRC Errors in Event Builder but not LRB. All errors from single LRB chip. See details below 6/11/2010 Sick
Deleted:
<
<
2152 FED_701 Tested. 6/1 OK
 
2153 FED_710 Tested. 6/1 OK
2154 FED_704 Installed on 12 Jul 2011 12 Jul 2011 OK
2155 *CERN Tested. 6/1 OK

Revision 3824 Jan 2012 - PhilLawson

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 79 to 79
 
2156 FED_714 Tested. 6/1 OK
2157 *CERN Tested. Warped board 6/1 OK/warped
2158 BU Problem: DSP FW version 0x301c reports as version 0x0 on this board. Can program manually with DCC2Tool.exe w/o issues. CRC of DSP FW reported by DCC2Tool.exe is correct. 6/1 (returned) Sick
Changed:
<
<
2159 FED_713 Tested. Removed from FED 713 8/18/11 fail LRB4 test 6/1 LRB4 sick
>
>
2159 FED_713 Tested. 8/18/11 fail LRB4 test, however, this LRB is not in use (no spigots attached to HTRs) 6/1 LRB4 sick
 
2160 904 Hospital Removed from FED 700 due to UERR on spigot 13 - 10/29/09. 6/1 Sick
2161 FED_708 Tested. 6/1 OK
2162 FED_716 Tested. 6/1 OK
Line: 122 to 122
  Changes:
Changed:
<
<		S/N 2159 fails LRB4 link/memory test in the pit as FED 713. PDL is swapping it out.
>
>		S/N 2159 fails LRB4 link/memory test in the pit as FED 713. PDL discovered that these spigots are not in use on this FED and opted not to swap out.
  -- EricHazen - 18 Aug 2011

Revision 3718 Aug 2011 - EricHazen

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 63 to 63
 
2140 FED_728 Tested. Initially 2 errors. 2nd time tested-no errors. Probably a wiring issue. 5/26 OK
2141 FED_723 Tested. 5/26 OK
2142 FED_701 Prior incident as different FED (3/24/10): Was removed when we had an issue where no HTRs were sending data. No other symptoms point to DCC failure 6/11/10 OK
Changed:
<
<
2143 BU Tested. Ethernet error(RJ 45). Was not fixed. Returned to BU 6/9/09. Accidentally shipped 5/26 Sick
>
>
2143 CERN Tested. Ethernet error(RJ 45). Was not fixed. Returned to BU 6/9/09. Tested/shipped back to CERN 8/18/11 OK
 
2144 FED_722 Tested. 5/26 OK
2145 904 Spares "Stops sending events down SLINK and goes to OFW at 80 kHz" . Tested OK by PDL 4/1/11 11/16 OK
2146 BU Tested. Pin9 of HTR14 RJ45 to U14 line open. Could be a PCB problem.   Sick
Line: 79 to 79
 
2156 FED_714 Tested. 6/1 OK
2157 *CERN Tested. Warped board 6/1 OK/warped
2158 BU Problem: DSP FW version 0x301c reports as version 0x0 on this board. Can program manually with DCC2Tool.exe w/o issues. CRC of DSP FW reported by DCC2Tool.exe is correct. 6/1 (returned) Sick
Changed:
<
<
2159 FED_713 Tested. 6/1 OK
>
>
2159 FED_713 Tested. Removed from FED 713 8/18/11 fail LRB4 test 6/1 LRB4 sick
 
2160 904 Hospital Removed from FED 700 due to UERR on spigot 13 - 10/29/09. 6/1 Sick
2161 FED_708 Tested. 6/1 OK
2162 FED_716 Tested. 6/1 OK
Line: 95 to 95
 
2172 904 Hospital CRC errros on LRB FPGA serving spigots 12,13,14. Elog: http://cmsonline.cern.ch/cms-elog/605813 12 Jul 2011 Sick
2173 FED_705 Tested. 6/9 OK
2174 FED_702 Tested. 6/9 OK
Changed:
<
<
2175 BU Tested. Broken LED-->VME.   Sick
>
>
2175 CERN Tested. Broken LED-->VME. Declared good, shipped to CERN 8/18/11 OK
 
2176 FED_703 Tested. 6/9 OK
2177 FED_709 Tested. 7/1 OK
2178 FED_700 Tested. Installed to replace 2160 - 10/29/09 7/1 OK
Line: 105 to 105
 
2182 *CERN Tested. 7/1 OK
2183 BU Tested. Ship to MN 2011-05-12 OK
2184 BU Tested. CRC error, SLINK error. "event size of 4800 words is unreasonable"   Sick
Changed:
<
<
2185 BU Tested.   OK
2186 BU Tested.   OK
>
>
2185 CERN Tested. Shipped to CERN 8/18/11 OK
2186 CERN Tested. Shipped to CERN 8/18/11 OK
 
2187 BU Board is warped. won't fit into crate.   Sick
2188 BU Tested. Ethernet RJ45 error.   Sick
Changed:
<
<
2189 BU Tested.   OK
>
>
2189 CERN Tested. Shipped to CERN 8/18/11 OK
 
2190 CERN Tested. 1/10 OK
2191 CERN Tested. 1/10 OK
2192 CERN Tested. 1/10 OK
2193 BU Returned ~3/10/10 w/ spigot 3 problem (CASTOR) 1/10 Sick
2194 BU Tested. 3/11/11 -- problems with spigots 3-5 (Eric/Dick) Sick
Changed:
<
<
2195 BU Tested.   OK
2196 BU Tested.   OK
>
>
2195 CERN Tested. Shipped to CERN 8/18/11 OK
2196 CERN Tested. Shipped to CERN 8/18/11 OK
 
2197 BU Tested.   OK
2198 BU Not ever tested?   ?
Line: 120 to 120
 
2197 BU Tested.   OK
2198 BU Not ever tested?   ?
Deleted:
<
<
 Changes:
Added:
>
>		 S/N 2159 fails LRB4 link/memory test in the pit as FED 713. PDL is swapping it out.

-- EricHazen - 18 Aug 2011

 S/N2163 LRB0 memory chip replaced. OK now. -- Main. Shouxiang Wu - 2 Aug 2011

Revision 3604 Aug 2011 - EricHazen

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 114 to 114
 
2191 CERN Tested. 1/10 OK
2192 CERN Tested. 1/10 OK
2193 BU Returned ~3/10/10 w/ spigot 3 problem (CASTOR) 1/10 Sick
Changed:
<
<
2194 CERN Tested. 3/11/11 -- problems with spigots 3-5 (Eric/Dick) Sick
>
>
2194 BU Tested. 3/11/11 -- problems with spigots 3-5 (Eric/Dick) Sick
 
2195 BU Tested.   OK
2196 BU Tested.   OK
2197 BU Tested.   OK

Revision 3502 Aug 2011 - SxWu

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 83 to 83
 
2160 904 Hospital Removed from FED 700 due to UERR on spigot 13 - 10/29/09. 6/1 Sick
2161 FED_708 Tested. 6/1 OK
2162 FED_716 Tested. 6/1 OK
Changed:
<
<
2163 904 Hospital CRC errors on LRB FPGA serving spigots 0,1,2. This was discovered after bringing up the detector from winter shutdown 26 Jan 2011 Sick
>
>
2163 BU DDR memory chip replaced 2 Aug 2011 OK
 
2164 FED_715 Tested. 6/9 OK
2165 FED_711 Tested. 6/9 OK
2166 FED_731 Tested. 6/9 OK
Line: 122 to 122
 

Changes:

Added:
>
>		S/N2163 LRB0 memory chip replaced. OK now. -- Main. Shouxiang Wu - 2 Aug 2011
  S/N 2172 showed CRC errors on LRB FPGA serving spigots 12,13,14. Replaced in USC on 12 Jul 2011. Installed in 904 and powered up to find all LRB chips reporting appropriate FW versions.

Revision 3419 Jul 2011 - PhilLawson

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 74 to 74
 
2152 904 Hospital CRC Errors in Event Builder but not LRB. All errors from single LRB chip. See details below 6/11/2010 Sick
2152 FED_701 Tested. 6/1 OK
2153 FED_710 Tested. 6/1 OK
Changed:
<
<
2154 *CERN Tested. 6/1 OK
>
>
2154 FED_704 Installed on 12 Jul 2011 12 Jul 2011 OK
 
2155 *CERN Tested. 6/1 OK
2156 FED_714 Tested. 6/1 OK
2157 *CERN Tested. Warped board 6/1 OK/warped
Line: 92 to 92
 
2169 FED_706 Tested. 6/9 OK
2170 BU Tested. CRC errors. Spigot zero bad?   Sick
2171 FED_717 Tested. 6/9 OK
Changed:
<
<
2172 FED_704 Tested. 6/9 OK
>
>
2172 904 Hospital CRC errros on LRB FPGA serving spigots 12,13,14. Elog: http://cmsonline.cern.ch/cms-elog/605813 12 Jul 2011 Sick
 
2173 FED_705 Tested. 6/9 OK
2174 FED_702 Tested. 6/9 OK
2175 BU Tested. Broken LED-->VME.   Sick
Line: 123 to 123
  Changes:
Added:
>
>		S/N 2172 showed CRC errors on LRB FPGA serving spigots 12,13,14. Replaced in USC on 12 Jul 2011. Installed in 904 and powered up to find all LRB chips reporting appropriate FW versions.

-- PhilLawson - 19 Jul 2011

 Ship 2179 and 2183 to FNAL and MN, respectively. Track# 1Z0159190193593478 and 1Z0159190190690681

Revision 3312 May 2011 - EricHazen

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 99 to 99
 
2176 FED_703 Tested. 6/9 OK
2177 FED_709 Tested. 7/1 OK
2178 FED_700 Tested. Installed to replace 2160 - 10/29/09 7/1 OK
Changed:
<
<
2179 BU Tested.   OK
>
>
2179 FNAL Tested. Ship to FNAL 2011-05-12 OK
 
2180 BU Tested. TTS link error. SLINK error.   Sick
2181 FED_727 Tested. 4/13/10 OK
2182 *CERN Tested. 7/1 OK
Changed:
<
<
2183 BU Tested.   OK
>
>
2183 BU Tested. Ship to MN 2011-05-12 OK
 
2184 BU Tested. CRC error, SLINK error. "event size of 4800 words is unreasonable"   Sick
2185 BU Tested.   OK
2186 BU Tested.   OK
Line: 123 to 123
  Changes:
Added:
>
>		Ship 2179 and 2183 to FNAL and MN, respectively. Track# 1Z0159190193593478 and 1Z0159190190690681

-- EricHazen - 12 May 2011

 Phil tested SN 2145 at CERN as follows:

Revision 3201 Apr 2011 - EricHazen

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 65 to 65
 
2142 FED_701 Prior incident as different FED (3/24/10): Was removed when we had an issue where no HTRs were sending data. No other symptoms point to DCC failure 6/11/10 OK
2143 BU Tested. Ethernet error(RJ 45). Was not fixed. Returned to BU 6/9/09. Accidentally shipped 5/26 Sick
2144 FED_722 Tested. 5/26 OK
Changed:
<
<
2145 *904 Hospital Stops sending events down SLINK and goes to OFW at 80 kHz 11/16 Sick
>
>
2145 904 Spares "Stops sending events down SLINK and goes to OFW at 80 kHz" . Tested OK by PDL 4/1/11 11/16 OK
 
2146 BU Tested. Pin9 of HTR14 RJ45 to U14 line open. Could be a PCB problem.   Sick
2147 BU Tested. Two broken LEDs, Ethernet error(RJ 45), and CRC error. R25 cold solder,D25 is also missing. Errors fixed as of 6/3   OK
2148 FED_721 Tested. 5/26 OK
Line: 123 to 123
  Changes:
Added:
>
>		Phil tested SN 2145 at CERN as follows: 

Installed HCAL DAQ version 10.4.6 (unrelated, needed for different test)
Altered FedkitTest_LTClistenToTTS_from_slot20 to take SLINK data from slot 20.
Blasted high rate events at DCC. Due to SLINK readout (with only CRC error checking), 
  effective rate was limited to 34 kHz since this DCC was providing TTS signal.
Readout 10E6 events at this rate with no SLINK errors. Good enough for me.

-- EricHazen - 01 Apr 2011

 

Revision 3111 Mar 2011 - EricHazen

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 114 to 114
 
2191 CERN Tested. 1/10 OK
2192 CERN Tested. 1/10 OK
2193 BU Returned ~3/10/10 w/ spigot 3 problem (CASTOR) 1/10 Sick
Changed:
<
<
2194 CERN Tested. 1/10 OK
>
>
2194 CERN Tested. 3/11/11 -- problems with spigots 3-5 (Eric/Dick) Sick
 
2195 BU Tested.   OK
2196 BU Tested.   OK
2197 BU Tested.   OK

Revision 3026 Jan 2011 - PhilLawson

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 83 to 83
 
2160 904 Hospital Removed from FED 700 due to UERR on spigot 13 - 10/29/09. 6/1 Sick
2161 FED_708 Tested. 6/1 OK
2162 FED_716 Tested. 6/1 OK
Changed:
<
<
2163 FED_709 Tested. 6/1 OK
>
>
2163 904 Hospital CRC errors on LRB FPGA serving spigots 0,1,2. This was discovered after bringing up the detector from winter shutdown 26 Jan 2011 Sick
 
2164 FED_715 Tested. 6/9 OK
2165 FED_711 Tested. 6/9 OK
2166 FED_731 Tested. 6/9 OK
Line: 97 to 97
 
2174 FED_702 Tested. 6/9 OK
2175 BU Tested. Broken LED-->VME.   Sick
2176 FED_703 Tested. 6/9 OK
Changed:
<
<
2177 *CERN Tested. 7/1 OK
>
>
2177 FED_709 Tested. 7/1 OK
 
2178 FED_700 Tested. Installed to replace 2160 - 10/29/09 7/1 OK
2179 BU Tested.   OK
2180 BU Tested. TTS link error. SLINK error.   Sick
Line: 123 to 123
  Changes:
Added:
>
>

-- PhilLawson - 26 Jan 2011

 
  • Updated list to reflect install of SN 2141 as FED 701 to replace sick DCC SN 2152.
    • SN 2152 evidenced communication problems between LRB and Event Builder chip
    • Details in eLog: 402680 on June 7 2010

Revision 2927 Oct 2010 - PhilLawson

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 62 to 62
 
2139 *CERN Tested. 5/26 OK
2140 FED_728 Tested. Initially 2 errors. 2nd time tested-no errors. Probably a wiring issue. 5/26 OK
2141 FED_723 Tested. 5/26 OK
Changed:
<
<
2142 FED_701 Prior incident as different FED (4/13/10): Was removed when we had an issue where no HTRs were sending data. No other symptoms point to DCC failure 6/11/10 OK
>
>
2142 FED_701 Prior incident as different FED (3/24/10): Was removed when we had an issue where no HTRs were sending data. No other symptoms point to DCC failure 6/11/10 OK
 
2143 BU Tested. Ethernet error(RJ 45). Was not fixed. Returned to BU 6/9/09. Accidentally shipped 5/26 Sick
2144 FED_722 Tested. 5/26 OK
2145 *904 Hospital Stops sending events down SLINK and goes to OFW at 80 kHz 11/16 Sick

Revision 2811 Jun 2010 - PhilLawson

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 62 to 62
 
2139 *CERN Tested. 5/26 OK
2140 FED_728 Tested. Initially 2 errors. 2nd time tested-no errors. Probably a wiring issue. 5/26 OK
2141 FED_723 Tested. 5/26 OK
Changed:
<
<
2142 *904 Hospital Was removed when we had an issue where no HTRs were sending data. No other symptoms point to DCC failure 4/13/10 OK
>
>
2142 FED_701 Prior incident as different FED (4/13/10): Was removed when we had an issue where no HTRs were sending data. No other symptoms point to DCC failure 6/11/10 OK
 
2143 BU Tested. Ethernet error(RJ 45). Was not fixed. Returned to BU 6/9/09. Accidentally shipped 5/26 Sick
2144 FED_722 Tested. 5/26 OK
2145 *904 Hospital Stops sending events down SLINK and goes to OFW at 80 kHz 11/16 Sick
Line: 71 to 71
 
2148 FED_721 Tested. 5/26 OK
2149 BU Tested. U0 soldering problem(most likely because U10 looks OK) Multiple lines to U10 without connection   Sick
2150 FED_719 Tested. 7/1 OK
Changed:
<
<
2151 FED_712 Tested. 6/1 OK
>
>
2152 904 Hospital CRC Errors in Event Builder but not LRB. All errors from single LRB chip. See details below 6/11/2010 Sick
 
2152 FED_701 Tested. 6/1 OK
2153 FED_710 Tested. 6/1 OK
2154 *CERN Tested. 6/1 OK
Line: 123 to 123
  Changes:
Added:
>
>
  • Updated list to reflect install of SN 2141 as FED 701 to replace sick DCC SN 2152.
    • SN 2152 evidenced communication problems between LRB and Event Builder chip
    • Details in eLog: 402680 on June 7 2010

-- PhilLawson - 11 Jun 2010

 
  • Updated list to reflect swap of SN 2142 as FED 727

-- PhilLawson - 13 Apr 2010

Revision 2713 Apr 2010 - PhilLawson

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 62 to 62
 
2139 *CERN Tested. 5/26 OK
2140 FED_728 Tested. Initially 2 errors. 2nd time tested-no errors. Probably a wiring issue. 5/26 OK
2141 FED_723 Tested. 5/26 OK
Changed:
<
<
2142 FED_727 Tested. 5/26 OK
>
>
2142 *904 Hospital Was removed when we had an issue where no HTRs were sending data. No other symptoms point to DCC failure 4/13/10 OK
 
2143 BU Tested. Ethernet error(RJ 45). Was not fixed. Returned to BU 6/9/09. Accidentally shipped 5/26 Sick
2144 FED_722 Tested. 5/26 OK
2145 *904 Hospital Stops sending events down SLINK and goes to OFW at 80 kHz 11/16 Sick
Line: 101 to 101
 
2178 FED_700 Tested. Installed to replace 2160 - 10/29/09 7/1 OK
2179 BU Tested.   OK
2180 BU Tested. TTS link error. SLINK error.   Sick
Changed:
<
<
2181 *CERN Tested. 7/1 OK
>
>
2181 FED_727 Tested. 4/13/10 OK
 
2182 *CERN Tested. 7/1 OK
2183 BU Tested.   OK
2184 BU Tested. CRC error, SLINK error. "event size of 4800 words is unreasonable"   Sick
Line: 123 to 123
  Changes:
Added:
>
>
  • Updated list to reflect swap of SN 2142 as FED 727

-- PhilLawson - 13 Apr 2010

 
  • Updated list per inventory from Dick. Location with * were confirmed at CERN per Dick's 12/14/09 inventory.

-- EricHazen - 14 Dec 2009

Revision 2612 Mar 2010 - EricHazen

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 110 to 110
 
2187 BU Board is warped. won't fit into crate.   Sick
2188 BU Tested. Ethernet RJ45 error.   Sick
2189 BU Tested.   OK
Changed:
<
<
2190 BU Tested.   OK
2191 BU Tested.   OK
2192 BU Tested.   OK
2193 BU Tested.   OK
2194 BU Tested.   OK
>
>
2190 CERN Tested. 1/10 OK
2191 CERN Tested. 1/10 OK
2192 CERN Tested. 1/10 OK
2193 BU Returned ~3/10/10 w/ spigot 3 problem (CASTOR) 1/10 Sick
2194 CERN Tested. 1/10 OK
 
2195 BU Tested.   OK
2196 BU Tested.   OK
2197 BU Tested.   OK

Revision 2514 Dec 2009 - EricHazen

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 23 to 23
  .... remainder of list truncated ...
Added:
>
>		Here is Dick Kellogg's list which may become the official one. For now, you have to check both.
 

Prototype Boards

S/N Location Notes
Changed:
<
<
2001 ??? Tested in MWGR 15
2002 ???  
2003 CERN - Bat 28 - cmsmoe6  
2004 CERN - Bat 904 - cmsmoe4  
>
>
2001 904 Tested in MWGR 15
2002 904  
2003 904  
2004 904  
 
2005 BU - Test stand  
2006 Whitman To be destructively tested for soldering temperature profiles
2007 BU Ethernet resistor replaced - re-test
Line: 47 to 50
 
S/N Location Notes Date shipped Status
2129 FED_730 Tested. 5/26 OK
Changed:
<
<
2130 904 Hospital Orbit number mismatches as FED 731 01-jul-2009 (removed) 5/26 Sick
>
>
2130 *904 Hospital Orbit number mismatches as FED 731 01-jul-2009 (removed) 5/26 Sick
 
2131 FED_720 Tested. 5/26 OK
2132 FED_718 Tested. 5/26 OK
2133 FED_729 Tested. 5/26 OK
Changed:
<
<
2134 CERN Tested. 5/26 OK
>
>
2134 BU Returned to BU because of alleged mis-matches 5/26 Sick
 
2135 FED_724 Tested. HTR13 LED broken. Now fixed. 5/26 OK
Changed:
<
<
2136 CERN Tested. 5/26 OK
>
>
2136 BU Shipped back to BU 6/9/09 per dick to CERN 5/26 OK
 
2137 FED_725 Tested. Initially 2 errors. 2nd time tested-no errors. Probably a wiring issue. 5/26 OK
2138 FED_726 Tested. 5/26 OK
Changed:
<
<
2139 CERN Tested. 5/26 OK
>
>
2139 *CERN Tested. 5/26 OK
 
2140 FED_728 Tested. Initially 2 errors. 2nd time tested-no errors. Probably a wiring issue. 5/26 OK
2141 FED_723 Tested. 5/26 OK
2142 FED_727 Tested. 5/26 OK
Changed:
<
<
2143 BU ? Tested. Ethernet error(RJ 45). Was not fixed. Accidentally shipped 5/26 Sick
>
>
2143 BU Tested. Ethernet error(RJ 45). Was not fixed. Returned to BU 6/9/09. Accidentally shipped 5/26 Sick
 
2144 FED_722 Tested. 5/26 OK
Changed:
<
<
2145 904 Hospital Stops sending events down SLINK and goes to OFW at 80 kHz 11/16 Sick
>
>
2145 *904 Hospital Stops sending events down SLINK and goes to OFW at 80 kHz 11/16 Sick
 
2146 BU Tested. Pin9 of HTR14 RJ45 to U14 line open. Could be a PCB problem.   Sick
2147 BU Tested. Two broken LEDs, Ethernet error(RJ 45), and CRC error. R25 cold solder,D25 is also missing. Errors fixed as of 6/3   OK
2148 FED_721 Tested. 5/26 OK
Line: 71 to 74
 
2151 FED_712 Tested. 6/1 OK
2152 FED_701 Tested. 6/1 OK
2153 FED_710 Tested. 6/1 OK
Changed:
<
<
2154 CERN Tested. 6/1 OK
2155 CERN Tested. 6/1 OK
>
>
2154 *CERN Tested. 6/1 OK
2155 *CERN Tested. 6/1 OK
 
2156 FED_714 Tested. 6/1 OK
Changed:
<
<
2157 CERN Tested. 6/1 OK
>
>
2157 *CERN Tested. Warped board 6/1 OK/warped
 
2158 BU Problem: DSP FW version 0x301c reports as version 0x0 on this board. Can program manually with DCC2Tool.exe w/o issues. CRC of DSP FW reported by DCC2Tool.exe is correct. 6/1 (returned) Sick
2159 FED_713 Tested. 6/1 OK
2160 904 Hospital Removed from FED 700 due to UERR on spigot 13 - 10/29/09. 6/1 Sick
Line: 94 to 97
 
2174 FED_702 Tested. 6/9 OK
2175 BU Tested. Broken LED-->VME.   Sick
2176 FED_703 Tested. 6/9 OK
Changed:
<
<
2177 CERN Tested. 7/1 OK
>
>
2177 *CERN Tested. 7/1 OK
 
2178 FED_700 Tested. Installed to replace 2160 - 10/29/09 7/1 OK
2179 BU Tested.   OK
2180 BU Tested. TTS link error. SLINK error.   Sick
Changed:
<
<
2181 CERN Tested. 7/1 OK
2182 CERN Tested. 7/1 OK
>
>
2181 *CERN Tested. 7/1 OK
2182 *CERN Tested. 7/1 OK
 
2183 BU Tested.   OK
2184 BU Tested. CRC error, SLINK error. "event size of 4800 words is unreasonable"   Sick
2185 BU Tested.   OK
Line: 119 to 122
 

Changes:

Deleted:
<
<
  • Logged in today and found FED 700 is now S/N 2160 (was previously 2001), FED 701 is now S/N 2152 (was previously 2002)
  • Problem with FED 710 & DSP FW 0x301c described above.
 
Changed:
<
<		-- PhilLawson - 26 Aug 2009
>
>
  • Updated list per inventory from Dick. Location with * were confirmed at CERN per Dick's 12/14/09 inventory.

-- EricHazen - 14 Dec 2009

  • Check and update a few mistakes in the list of installed DCC2

-- EricHazen - 11 Dec 2009

 
  • FED 719 (S/N 2145) was consistently going to OFW at 80 kHz. No events being sent down SLINK. Replaced DCC with S/N 2150

-- PhilLawson - 16 Nov 2009

Changed:
<
<
  • Check and update a few mistakes in the list of installed DCC2
>
>
  • Logged in today and found FED 700 is now S/N 2160 (was previously 2001), FED 701 is now S/N 2152 (was previously 2002)
  • Problem with FED 710 & DSP FW 0x301c described above.
 
Changed:
<
<		-- EricHazen - 11 Dec 2009
>
>		-- PhilLawson - 26 Aug 2009

Revision 2411 Dec 2009 - EricHazen

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 42 to 42
 The production board serial numbers start with 2129 as shown below. On the PCB, the binary "jumpers" (actually cut traces) start with "10000001".
Changed:
<
<
S/N Location Notes Date shipped
2129 FED_730 Tested. 5/26
2130 CERN Tested. 5/26
2131 FED_720 Tested. 5/26
2132 FED_718 Tested. 5/26
2133 FED_729 Tested. 5/26
2134 CERN Tested. 5/26
2135 FED_724 Tested. HTR13 LED broken. Now fixed. 5/26
2136 CERN Tested. 5/26
2137 FED_725 Tested. Initially 2 errors. 2nd time tested-no errors. Probably a wiring issue. 5/26
2138 FED_726 Tested. 5/26
2139 CERN Tested. 5/26
2140 FED_728 Tested. Initially 2 errors. 2nd time tested-no errors. Probably a wiring issue. 5/26
2141 FED_723 Tested. 5/26
2142 FED_727 Tested. 5/26
2143 BU Tested. Ethernet error(RJ 45). Was not fixed. Accidentally shipped 5/26
2144 FED_722 Tested. 5/26
2145 904 Hospital Stops sending events down SLINK and goes to OFW at 80 kHz 11/16
2146 BU Tested. Pin9 of HTR14 RJ45 to U14 line open. Could be a PCB problem.  
2147 BU Tested. Two broken LEDs, Ethernet error(RJ 45), and CRC error. R25 cold solder,D25 is also missing. Errors fixed as of 6/3
2148 FED_721 Tested. 5/26
2149 BU Tested. U0 soldering problem(most likely because U10 looks OK) Multiple lines to U10 without connection
2150 FED_719 Tested. 7/1
2151 CERN Tested. 6/1
2152 FED_701 Tested. 6/1
2153 FED_710 Tested. 6/1
2154 CERN Tested. 6/1
2155 CERN Tested. 6/1
2156 FED_714 Tested. 6/1
2157 CERN Tested. 6/1
2158 904 Problem: DSP FW version 0x301c reports as version 0x0 on this board. Can program manually with DCC2Tool.exe w/o issues. CRC of DSP FW reported by DCC2Tool.exe is correct. 6/1
2159 CERN Tested. 6/1
2160 904 Hospital Removed from FED 700 due to UERR on spigot 13 - 10/29/09. 6/1
2161 FED_708 Tested. 6/1
2162 FED_716 Tested. 6/1
2163 FED_709 Tested. 6/1
2164 FED_715 Tested. 6/9
2165 FED_711 Tested. 6/9
2166 FED_731 Tested. 6/9
2167 BU Tested. Spigot CRC error/SLINK error  
2168 FED_707 Tested. 6/9
2169 FED_706 Tested. 6/9
2170 BU Tested. CRC errors. Spigot zero bad?  
2171 FED_717 Tested. 6/9
2172 FED_704 Tested. 6/9
2173 FED_705 Tested. 6/9
2174 FED_702 Tested. 6/9
2175 BU Tested. Broken LED-->VME.  
2176 FED_703 Tested. 6/9
2177 CERN Tested. 7/1
2178 FED_700 Tested. Installed to replace 2160 - 10/29/09 7/1
2179 BU Tested.  
2180 BU Tested. TTS link error. SLINK error.  
2181 CERN Tested. 7/1
2182 CERN Tested. 7/1
2183 BU Tested.  
2184 BU Tested. CRC error, SLINK error. "event size of 4800 words is unreasonable"  
2185 BU Tested.  
2186 BU Tested.  
2187 BU Board is warped. won't fit into crate.  
2188 BU Tested. Ethernet RJ45 error.  
2189 BU Tested.  
2190 BU Tested.  
2191 BU Tested.  
2192 BU Tested.  
2193 BU Tested.  
2194 BU Tested.  
2195 BU Tested.  
2196 BU Tested.  
2197 BU Tested.  
>
>		Note that you can sort the table below by clicking the column headings. Sort by Location for an easy way to check how many boards are where.
 
Added:
>
>
S/N Location Notes Date shipped Status
2129 FED_730 Tested. 5/26 OK
2130 904 Hospital Orbit number mismatches as FED 731 01-jul-2009 (removed) 5/26 Sick
2131 FED_720 Tested. 5/26 OK
2132 FED_718 Tested. 5/26 OK
2133 FED_729 Tested. 5/26 OK
2134 CERN Tested. 5/26 OK
2135 FED_724 Tested. HTR13 LED broken. Now fixed. 5/26 OK
2136 CERN Tested. 5/26 OK
2137 FED_725 Tested. Initially 2 errors. 2nd time tested-no errors. Probably a wiring issue. 5/26 OK
2138 FED_726 Tested. 5/26 OK
2139 CERN Tested. 5/26 OK
2140 FED_728 Tested. Initially 2 errors. 2nd time tested-no errors. Probably a wiring issue. 5/26 OK
2141 FED_723 Tested. 5/26 OK
2142 FED_727 Tested. 5/26 OK
2143 BU ? Tested. Ethernet error(RJ 45). Was not fixed. Accidentally shipped 5/26 Sick
2144 FED_722 Tested. 5/26 OK
2145 904 Hospital Stops sending events down SLINK and goes to OFW at 80 kHz 11/16 Sick
2146 BU Tested. Pin9 of HTR14 RJ45 to U14 line open. Could be a PCB problem.   Sick
2147 BU Tested. Two broken LEDs, Ethernet error(RJ 45), and CRC error. R25 cold solder,D25 is also missing. Errors fixed as of 6/3   OK
2148 FED_721 Tested. 5/26 OK
2149 BU Tested. U0 soldering problem(most likely because U10 looks OK) Multiple lines to U10 without connection   Sick
2150 FED_719 Tested. 7/1 OK
2151 FED_712 Tested. 6/1 OK
2152 FED_701 Tested. 6/1 OK
2153 FED_710 Tested. 6/1 OK
2154 CERN Tested. 6/1 OK
2155 CERN Tested. 6/1 OK
2156 FED_714 Tested. 6/1 OK
2157 CERN Tested. 6/1 OK
2158 BU Problem: DSP FW version 0x301c reports as version 0x0 on this board. Can program manually with DCC2Tool.exe w/o issues. CRC of DSP FW reported by DCC2Tool.exe is correct. 6/1 (returned) Sick
2159 FED_713 Tested. 6/1 OK
2160 904 Hospital Removed from FED 700 due to UERR on spigot 13 - 10/29/09. 6/1 Sick
2161 FED_708 Tested. 6/1 OK
2162 FED_716 Tested. 6/1 OK
2163 FED_709 Tested. 6/1 OK
2164 FED_715 Tested. 6/9 OK
2165 FED_711 Tested. 6/9 OK
2166 FED_731 Tested. 6/9 OK
2167 BU Tested. Spigot CRC error/SLINK error   Sick
2168 FED_707 Tested. 6/9 OK
2169 FED_706 Tested. 6/9 OK
2170 BU Tested. CRC errors. Spigot zero bad?   Sick
2171 FED_717 Tested. 6/9 OK
2172 FED_704 Tested. 6/9 OK
2173 FED_705 Tested. 6/9 OK
2174 FED_702 Tested. 6/9 OK
2175 BU Tested. Broken LED-->VME.   Sick
2176 FED_703 Tested. 6/9 OK
2177 CERN Tested. 7/1 OK
2178 FED_700 Tested. Installed to replace 2160 - 10/29/09 7/1 OK
2179 BU Tested.   OK
2180 BU Tested. TTS link error. SLINK error.   Sick
2181 CERN Tested. 7/1 OK
2182 CERN Tested. 7/1 OK
2183 BU Tested.   OK
2184 BU Tested. CRC error, SLINK error. "event size of 4800 words is unreasonable"   Sick
2185 BU Tested.   OK
2186 BU Tested.   OK
2187 BU Board is warped. won't fit into crate.   Sick
2188 BU Tested. Ethernet RJ45 error.   Sick
2189 BU Tested.   OK
2190 BU Tested.   OK
2191 BU Tested.   OK
2192 BU Tested.   OK
2193 BU Tested.   OK
2194 BU Tested.   OK
2195 BU Tested.   OK
2196 BU Tested.   OK
2197 BU Tested.   OK
2198 BU Not ever tested?   ?
 
Deleted:
<
<		 EricHazen - 15 Apr 2009
  Changes:
  • Logged in today and found FED 700 is now S/N 2160 (was previously 2001), FED 701 is now S/N 2152 (was previously 2002)
Line: 125 to 127
 
  • FED 719 (S/N 2145) was consistently going to OFW at 80 kHz. No events being sent down SLINK. Replaced DCC with S/N 2150

-- PhilLawson - 16 Nov 2009

Added:
>
>
  • Check and update a few mistakes in the list of installed DCC2

-- EricHazen - 11 Dec 2009

Revision 2316 Nov 2009 - PhilLawson

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 59 to 59
 
2142 FED_727 Tested. 5/26
2143 BU Tested. Ethernet error(RJ 45). Was not fixed. Accidentally shipped 5/26
2144 FED_722 Tested. 5/26
Changed:
<
<
2145 FED_719 Tested. 5/26
>
>
2145 904 Hospital Stops sending events down SLINK and goes to OFW at 80 kHz 11/16
 
2146 BU Tested. Pin9 of HTR14 RJ45 to U14 line open. Could be a PCB problem.  
2147 BU Tested. Two broken LEDs, Ethernet error(RJ 45), and CRC error. R25 cold solder,D25 is also missing. Errors fixed as of 6/3
2148 FED_721 Tested. 5/26
2149 BU Tested. U0 soldering problem(most likely because U10 looks OK) Multiple lines to U10 without connection
Changed:
<
<
2150 CERN Tested. 7/1
>
>
2150 FED_719 Tested. 7/1
 
2151 CERN Tested. 6/1
2152 FED_701 Tested. 6/1
2153 FED_710 Tested. 6/1
Line: 117 to 117
  EricHazen - 15 Apr 2009

Changes:

Changed:
<
<		Logged in today and found FED 700 is now S/N 2160 (was previously 2001), FED 701 is now S/N 2152 (was previously 2002) Problem with FED 710 & DSP FW 0x301c described above.
>
>
  • Logged in today and found FED 700 is now S/N 2160 (was previously 2001), FED 701 is now S/N 2152 (was previously 2002)
  • Problem with FED 710 & DSP FW 0x301c described above.
  -- PhilLawson - 26 Aug 2009 \ No newline at end of file
Added:
>
>
  • FED 719 (S/N 2145) was consistently going to OFW at 80 kHz. No events being sent down SLINK. Replaced DCC with S/N 2150

-- PhilLawson - 16 Nov 2009

Revision 2229 Oct 2009 - EricHazen

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 74 to 74
 
2157 CERN Tested. 6/1
2158 904 Problem: DSP FW version 0x301c reports as version 0x0 on this board. Can program manually with DCC2Tool.exe w/o issues. CRC of DSP FW reported by DCC2Tool.exe is correct. 6/1
2159 CERN Tested. 6/1
Changed:
<
<
2160 FED_700 Tested. 6/1
>
>
2160 904 Hospital Removed from FED 700 due to UERR on spigot 13 - 10/29/09. 6/1
 
2161 FED_708 Tested. 6/1
2162 FED_716 Tested. 6/1
2163 FED_709 Tested. 6/1
Line: 92 to 92
 
2175 BU Tested. Broken LED-->VME.  
2176 FED_703 Tested. 6/9
2177 CERN Tested. 7/1
Changed:
<
<
2178 CERN Tested. 7/1
>
>
2178 FED_700 Tested. Installed to replace 2160 - 10/29/09 7/1
 
2179 BU Tested.  
2180 BU Tested. TTS link error. SLINK error.  
2181 CERN Tested. 7/1

Revision 2103 Sep 2009 - PhilLawson

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 67 to 67
 
2150 CERN Tested. 7/1
2151 CERN Tested. 6/1
2152 FED_701 Tested. 6/1
Changed:
<
<
2153 CERN Tested. 6/1
>
>
2153 FED_710 Tested. 6/1
 
2154 CERN Tested. 6/1
2155 CERN Tested. 6/1
2156 FED_714 Tested. 6/1
2157 CERN Tested. 6/1
Changed:
<
<
2158 FED_710 Problem: DSP FW version 0x301c reports as version 0x0 on this board. Can program manually with DCC2Tool.exe w/o issues. CRC of DSP FW reported by DCC2Tool.exe is correct. 6/1
>
>
2158 904 Problem: DSP FW version 0x301c reports as version 0x0 on this board. Can program manually with DCC2Tool.exe w/o issues. CRC of DSP FW reported by DCC2Tool.exe is correct. 6/1
 
2159 CERN Tested. 6/1
2160 FED_700 Tested. 6/1
2161 FED_708 Tested. 6/1

Revision 2026 Aug 2009 - PhilLawson

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 72 to 72
 
2155 CERN Tested. 6/1
2156 FED_714 Tested. 6/1
2157 CERN Tested. 6/1
Changed:
<
<
2158 FED_710 Tested. 6/1
>
>
2158 FED_710 Problem: DSP FW version 0x301c reports as version 0x0 on this board. Can program manually with DCC2Tool.exe w/o issues. CRC of DSP FW reported by DCC2Tool.exe is correct. 6/1
 
2159 CERN Tested. 6/1
2160 FED_700 Tested. 6/1
2161 FED_708 Tested. 6/1
Line: 118 to 118
  Changes: Logged in today and found FED 700 is now S/N 2160 (was previously 2001), FED 701 is now S/N 2152 (was previously 2002)
Added:
>
>		Problem with FED 710 & DSP FW 0x301c described above.
 -- PhilLawson - 26 Aug 2009 \ No newline at end of file

Revision 1926 Aug 2009 - PhilLawson

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 26 to 26
 

Prototype Boards

S/N Location Notes
Changed:
<
<
2001 USC FED 700 Tested in MWGR 15
2002 USC FED 701  
>
>
2001 ??? Tested in MWGR 15
2002 ???  
 
2003 CERN - Bat 28 - cmsmoe6  
2004 CERN - Bat 904 - cmsmoe4  
2005 BU - Test stand  
Line: 66 to 66
 
2149 BU Tested. U0 soldering problem(most likely because U10 looks OK) Multiple lines to U10 without connection
2150 CERN Tested. 7/1
2151 CERN Tested. 6/1
Changed:
<
<
2152 CERN Tested. 6/1
>
>
2152 FED_701 Tested. 6/1
 
2153 CERN Tested. 6/1
2154 CERN Tested. 6/1
2155 CERN Tested. 6/1
Line: 74 to 74
 
2157 CERN Tested. 6/1
2158 FED_710 Tested. 6/1
2159 CERN Tested. 6/1
Changed:
<
<
2160 CERN Tested. 6/1
>
>
2160 FED_700 Tested. 6/1
 
2161 FED_708 Tested. 6/1
2162 FED_716 Tested. 6/1
2163 FED_709 Tested. 6/1
Line: 115 to 115
 

EricHazen - 15 Apr 2009 \ No newline at end of file

Added:
>
>		 Changes: Logged in today and found FED 700 is now S/N 2160 (was previously 2001), FED 701 is now S/N 2152 (was previously 2002) -- PhilLawson - 26 Aug 2009
 \ No newline at end of file

Revision 1809 Jul 2009 - JasonStJohn

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 11 to 11
  (log on to a head node, i.e. cmsusr1 etc)
Changed:
<
<		$ cd ~hazen/GetStatus
>
>		$ cd ~ehazen/GetStatus
 $ ./getAllVersions.sh | ./parseVersions.pl

Crate Bus Slot Xilinx LRB VME S/N FED

Revision 1709 Jul 2009 - EricHazen

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
Changed:
<
<		10 Prototype boards with red front panels were manufactured in early 2009. These boards are not compatible with
>
>		10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to
 the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.

Boards are numbered in decimal starting with 2001 for the first prototype up to a maximum possible number of 2255. The first digit is always '2'. The other three digits represent the decimal equivalent of the binary value set by cutting jumpers on the PCB.

Added:
>
>		You can find out which board is where in the pit as follows:

(log on to a head node, i.e. cmsusr1 etc) 

$ cd ~hazen/GetStatus
$ ./getAllVersions.sh | ./parseVersions.pl

 Crate  Bus    Slot   Xilinx     LRB        VME    S/N  FED
 ====================================
     4  caen:0 10     0x3018     0x010a     0x0104 2001 700
     4  caen:0 20     0x3018     0x010a     0x0104 2002 701
     0  caen:1 10     0x3018     0x010a     0x0104 2174 702
     0  caen:1 20     0x3018     0x010a     0x0104 2176 703
       .... remainder of list truncated ...
 

Prototype Boards

S/N Location Notes
Changed:
<
<
2001 CERN - Bat 904 - lxcmdtest3 Tested in MWGR 15
2002 BU  
>
>
2001 USC FED 700 Tested in MWGR 15
2002 USC FED 701  
 
2003 CERN - Bat 28 - cmsmoe6  
2004 CERN - Bat 904 - cmsmoe4  
2005 BU - Test stand  
Line: 27 to 43
 On the PCB, the binary "jumpers" (actually cut traces) start with "10000001".

S/N Location Notes Date shipped
Changed:
<
<
2129 CERN Tested. 5/26
>
>
2129 FED_730 Tested. 5/26
 
2130 CERN Tested. 5/26
Changed:
<
<
2131 CERN Tested. 5/26
2132 CERN Tested. 5/26
2133 CERN Tested. 5/26
>
>
2131 FED_720 Tested. 5/26
2132 FED_718 Tested. 5/26
2133 FED_729 Tested. 5/26
 
2134 CERN Tested. 5/26
Changed:
<
<
2135 CERN Tested. HTR13 LED broken. Now fixed. 5/26
>
>
2135 FED_724 Tested. HTR13 LED broken. Now fixed. 5/26
 
2136 CERN Tested. 5/26
Changed:
<
<
2137 CERN Tested. Initially 2 errors. 2nd time tested-no errors. Probably a wiring issue. 5/26
2138 CERN Tested. 5/26
>
>
2137 FED_725 Tested. Initially 2 errors. 2nd time tested-no errors. Probably a wiring issue. 5/26
2138 FED_726 Tested. 5/26
 
2139 CERN Tested. 5/26
Changed:
<
<
2140 CERN Tested. Initially 2 errors. 2nd time tested-no errors. Probably a wiring issue. 5/26
2141 CERN Tested. 5/26
2142 CERN Tested. 5/26
>
>
2140 FED_728 Tested. Initially 2 errors. 2nd time tested-no errors. Probably a wiring issue. 5/26
2141 FED_723 Tested. 5/26
2142 FED_727 Tested. 5/26
 
2143 BU Tested. Ethernet error(RJ 45). Was not fixed. Accidentally shipped 5/26
Changed:
<
<
2144 CERN Tested. 5/26
2145 CERN Tested. 5/26
>
>
2144 FED_722 Tested. 5/26
2145 FED_719 Tested. 5/26
 
2146 BU Tested. Pin9 of HTR14 RJ45 to U14 line open. Could be a PCB problem.  
2147 BU Tested. Two broken LEDs, Ethernet error(RJ 45), and CRC error. R25 cold solder,D25 is also missing. Errors fixed as of 6/3
Changed:
<
<
2148 CERN Tested. 5/26
>
>
2148 FED_721 Tested. 5/26
 
2149 BU Tested. U0 soldering problem(most likely because U10 looks OK) Multiple lines to U10 without connection
2150 CERN Tested. 7/1
2151 CERN Tested. 6/1
Line: 54 to 70
 
2153 CERN Tested. 6/1
2154 CERN Tested. 6/1
2155 CERN Tested. 6/1
Changed:
<
<
2156 CERN Tested. 6/1
>
>
2156 FED_714 Tested. 6/1
 
2157 CERN Tested. 6/1
Changed:
<
<
2158 CERN Tested. 6/1
>
>
2158 FED_710 Tested. 6/1
 
2159 CERN Tested. 6/1
2160 CERN Tested. 6/1
Changed:
<
<
2161 CERN Tested. 6/1
2162 CERN Tested. 6/1
2163 CERN Tested. 6/1
2164 CERN Tested. 6/9
2165 CERN Tested. 6/9
2166 CERN Tested. 6/9
>
>
2161 FED_708 Tested. 6/1
2162 FED_716 Tested. 6/1
2163 FED_709 Tested. 6/1
2164 FED_715 Tested. 6/9
2165 FED_711 Tested. 6/9
2166 FED_731 Tested. 6/9
 
2167 BU Tested. Spigot CRC error/SLINK error  
Changed:
<
<
2168 CERN Tested. 6/9
2169 CERN Tested. 6/9
>
>
2168 FED_707 Tested. 6/9
2169 FED_706 Tested. 6/9
 
2170 BU Tested. CRC errors. Spigot zero bad?  
Changed:
<
<
2171 CERN Tested. 6/9
2172 CERN Tested. 6/9
2173 CERN Tested. 6/9
2174 CERN Tested. 6/9
>
>
2171 FED_717 Tested. 6/9
2172 FED_704 Tested. 6/9
2173 FED_705 Tested. 6/9
2174 FED_702 Tested. 6/9
 
2175 BU Tested. Broken LED-->VME.  
Changed:
<
<
2176 CERN Tested. 6/9
>
>
2176 FED_703 Tested. 6/9
 
2177 CERN Tested. 7/1
2178 CERN Tested. 7/1
2179 BU Tested.  

Revision 1606 Jul 2009 - AshleyRubinstein

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not compatible with the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 48 to 48
 
2147 BU Tested. Two broken LEDs, Ethernet error(RJ 45), and CRC error. R25 cold solder,D25 is also missing. Errors fixed as of 6/3
2148 CERN Tested. 5/26
2149 BU Tested. U0 soldering problem(most likely because U10 looks OK) Multiple lines to U10 without connection
Changed:
<
<
2150 BU Tested.  
>
>
2150 CERN Tested. 7/1
 
2151 CERN Tested. 6/1
2152 CERN Tested. 6/1
2153 CERN Tested. 6/1
Line: 62 to 62
 
2161 CERN Tested. 6/1
2162 CERN Tested. 6/1
2163 CERN Tested. 6/1
Changed:
<
<
2164 BU Tested. 6/9
2165 BU Tested. 6/9
2166 BU Tested. 6/9
>
>
2164 CERN Tested. 6/9
2165 CERN Tested. 6/9
2166 CERN Tested. 6/9
 
2167 BU Tested. Spigot CRC error/SLINK error  
Changed:
<
<
2168 BU Tested. 6/9
2169 BU Tested. 6/9
>
>
2168 CERN Tested. 6/9
2169 CERN Tested. 6/9
 
2170 BU Tested. CRC errors. Spigot zero bad?  
Changed:
<
<
2171 BU Tested. 6/9
2172 BU Tested. 6/9
2173 BU Tested. 6/9
2174 BU Tested. 6/9
>
>
2171 CERN Tested. 6/9
2172 CERN Tested. 6/9
2173 CERN Tested. 6/9
2174 CERN Tested. 6/9
 
2175 BU Tested. Broken LED-->VME.  
Changed:
<
<
2176 BU Tested. 6/9
2177 BU Tested.  
2178 BU Tested.  
2179 BU Not yet tested..  
>
>
2176 CERN Tested. 6/9
2177 CERN Tested. 7/1
2178 CERN Tested. 7/1
2179 BU Tested.  
 
2180 BU Tested. TTS link error. SLINK error.  
Changed:
<
<
2181 BU Tested.  
2182 BU Tested.  
>
>
2181 CERN Tested. 7/1
2182 CERN Tested. 7/1
 
2183 BU Tested.  
2184 BU Tested. CRC error, SLINK error. "event size of 4800 words is unreasonable"  
2185 BU Tested.  
2186 BU Tested.  
2187 BU Board is warped. won't fit into crate.  
2188 BU Tested. Ethernet RJ45 error.  
Changed:
<
<
2189      
2190      
2191      
2192      
2193      
2194      
2195      
2196      
2197      
2198      
>
>
2189 BU Tested.  
2190 BU Tested.  
2191 BU Tested.  
2192 BU Tested.  
2193 BU Tested.  
2194 BU Tested.  
2195 BU Tested.  
2196 BU Tested.  
2197 BU Tested.  
 

Revision 1502 Jul 2009 - EricHazen

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not compatible with the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 87 to 87
 
2186 BU Tested.  
2187 BU Board is warped. won't fit into crate.  
2188 BU Tested. Ethernet RJ45 error.  
Added:
>
>
2189      
2190      
2191      
2192      
2193      
2194      
2195      
2196      
2197      
2198      
 

EricHazen - 15 Apr 2009 \ No newline at end of file

Revision 1401 Jul 2009 - AshleyRubinstein

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not compatible with the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 79 to 79
 
2178 BU Tested.  
2179 BU Not yet tested..  
2180 BU Tested. TTS link error. SLINK error.  
Added:
>
>
2181 BU Tested.  
2182 BU Tested.  
2183 BU Tested.  
2184 BU Tested. CRC error, SLINK error. "event size of 4800 words is unreasonable"  
2185 BU Tested.  
2186 BU Tested.  
2187 BU Board is warped. won't fit into crate.  
2188 BU Tested. Ethernet RJ45 error.  
 

EricHazen - 15 Apr 2009 \ No newline at end of file

Revision 1310 Jun 2009 - AshleyRubinstein

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not compatible with the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 62 to 62
 
2161 CERN Tested. 6/1
2162 CERN Tested. 6/1
2163 CERN Tested. 6/1
Changed:
<
<
2164 BU Tested.  
2165 BU Tested.  
2166 BU Tested.  
>
>
2164 BU Tested. 6/9
2165 BU Tested. 6/9
2166 BU Tested. 6/9
 
2167 BU Tested. Spigot CRC error/SLINK error  
Changed:
<
<
2168 BU Tested.  
2169 BU Tested.  
2170 BU Tested.  
2171 BU Tested. CRC errors. Spigot zero bad?  
>
>
2168 BU Tested. 6/9
2169 BU Tested. 6/9
2170 BU Tested. CRC errors. Spigot zero bad?  
2171 BU Tested. 6/9
2172 BU Tested. 6/9
2173 BU Tested. 6/9
2174 BU Tested. 6/9
2175 BU Tested. Broken LED-->VME.  
2176 BU Tested. 6/9
2177 BU Tested.  
2178 BU Tested.  
2179 BU Not yet tested..  
2180 BU Tested. TTS link error. SLINK error.  
  EricHazen - 15 Apr 2009

Revision 1208 Jun 2009 - AshleyRubinstein

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not compatible with the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 62 to 62
 
2161 CERN Tested. 6/1
2162 CERN Tested. 6/1
2163 CERN Tested. 6/1
Added:
>
>
2164 BU Tested.  
2165 BU Tested.  
2166 BU Tested.  
2167 BU Tested. Spigot CRC error/SLINK error  
2168 BU Tested.  
2169 BU Tested.  
2170 BU Tested.  
2171 BU Tested. CRC errors. Spigot zero bad?  
  EricHazen - 15 Apr 2009

Revision 1104 Jun 2009 - AshleyRubinstein

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not compatible with the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 45 to 45
 
2144 CERN Tested. 5/26
2145 CERN Tested. 5/26
2146 BU Tested. Pin9 of HTR14 RJ45 to U14 line open. Could be a PCB problem.  
Changed:
<
<
2147 BU Tested. Two broken LEDs, Ethernet error(RJ 45), and CRC error. Errors fixed as of 6/3
>
>
2147 BU Tested. Two broken LEDs, Ethernet error(RJ 45), and CRC error. R25 cold solder,D25 is also missing. Errors fixed as of 6/3
 
2148 CERN Tested. 5/26
2149 BU Tested. U0 soldering problem(most likely because U10 looks OK) Multiple lines to U10 without connection
2150 BU Tested.  
Changed:
<
<
2151 BU Tested. 6/1
2152 BU Tested. 6/1
2153 BU Tested. 6/1
2154 BU Tested. 6/1
2155 BU Tested. 6/1
2156 BU Tested. 6/1
2157 BU Tested. 6/1
2158 BU Tested. 6/1
2159 BU Tested. 6/1
2160 BU Tested. 6/1
2161 BU Tested. 6/1
2162 BU Tested. 6/1
2163 BU Tested. 6/1
>
>
2151 CERN Tested. 6/1
2152 CERN Tested. 6/1
2153 CERN Tested. 6/1
2154 CERN Tested. 6/1
2155 CERN Tested. 6/1
2156 CERN Tested. 6/1
2157 CERN Tested. 6/1
2158 CERN Tested. 6/1
2159 CERN Tested. 6/1
2160 CERN Tested. 6/1
2161 CERN Tested. 6/1
2162 CERN Tested. 6/1
2163 CERN Tested. 6/1
  EricHazen - 15 Apr 2009 \ No newline at end of file

Revision 1003 Jun 2009 - AshleyRubinstein

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not compatible with the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 18 to 18
 
2006 Whitman To be destructively tested for soldering temperature profiles
2007 BU Ethernet resistor replaced - re-test
2008 BU Ethernet resistor replaced - re-test
Changed:
<
<
2009 BU Ethernet resistor replaced - re-test
>
>
2009 BU Tested. No errors
 
2010 BU  

Production Boards

Line: 45 to 45
 
2144 CERN Tested. 5/26
2145 CERN Tested. 5/26
2146 BU Tested. Pin9 of HTR14 RJ45 to U14 line open. Could be a PCB problem.  
Changed:
<
<
2147 BU Tested. Two broken LEDs, Ethernet error(RJ 45), and CRC error. As of 6/3- still getting a CRC error! Ethernet/LEDs fixed.
>
>
2147 BU Tested. Two broken LEDs, Ethernet error(RJ 45), and CRC error. Errors fixed as of 6/3
 
2148 CERN Tested. 5/26
2149 BU Tested. U0 soldering problem(most likely because U10 looks OK) Multiple lines to U10 without connection
2150 BU Tested.  

Revision 903 Jun 2009 - AshleyRubinstein

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not compatible with the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 24 to 24
 

Production Boards

The production board serial numbers start with 2129 as shown below.

Changed:
<
<		On the PCB, the binary "jumpers" (actually cut traces) star with "10000001".
>
>		On the PCB, the binary "jumpers" (actually cut traces) start with "10000001".
 
S/N Location Notes Date shipped
2129 CERN Tested. 5/26
Line: 44 to 44
 
2143 BU Tested. Ethernet error(RJ 45). Was not fixed. Accidentally shipped 5/26
2144 CERN Tested. 5/26
2145 CERN Tested. 5/26
Changed:
<
<
2146 BU Tested. SLINK and CRC errors.  
2147 BU Tested. Two broken LEDs, Ethernet error(RJ 45), and CRC error.
>
>
2146 BU Tested. Pin9 of HTR14 RJ45 to U14 line open. Could be a PCB problem.  
2147 BU Tested. Two broken LEDs, Ethernet error(RJ 45), and CRC error. As of 6/3- still getting a CRC error! Ethernet/LEDs fixed.
 
2148 CERN Tested. 5/26
Changed:
<
<
2149 BU Tested. DSP error
>
>
2149 BU Tested. U0 soldering problem(most likely because U10 looks OK) Multiple lines to U10 without connection
 
2150 BU Tested.  
2151 BU Tested. 6/1
2152 BU Tested. 6/1

Revision 803 Jun 2009 - EricHazen

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not compatible with the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 16 to 16
 
2004 CERN - Bat 904 - cmsmoe4  
2005 BU - Test stand  
2006 Whitman To be destructively tested for soldering temperature profiles
Changed:
<
<
2007 BU  
2008 BU  
2009 BU  
>
>
2007 BU Ethernet resistor replaced - re-test
2008 BU Ethernet resistor replaced - re-test
2009 BU Ethernet resistor replaced - re-test
 
2010 BU  

Production Boards

Revision 702 Jun 2009 - AshleyRubinstein

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not compatible with the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 27 to 27
 On the PCB, the binary "jumpers" (actually cut traces) star with "10000001".

S/N Location Notes Date shipped
Changed:
<
<
2129 BU Tested. 5/26
2130 BU Tested. 5/26
2131 BU Tested. 5/26
2132 BU Tested. 5/26
2133 BU Tested. 5/26
2134 BU Tested. 5/26
2135 BU Tested. HTR13 LED broken. Now fixed. 5/26
2136 BU Tested. 5/26
2137 BU Tested. Initially 2 errors. 2nd time tested-no errors. Probably a wiring issue. 5/26
2138 BU Tested. 5/26
2139 BU Tested. 5/26
2140 BU Tested. Initially 2 errors. 2nd time tested-no errors. Probably a wiring issue. 5/26
2141 BU Tested. 5/26
2142 BU Tested. 5/26
>
>
2129 CERN Tested. 5/26
2130 CERN Tested. 5/26
2131 CERN Tested. 5/26
2132 CERN Tested. 5/26
2133 CERN Tested. 5/26
2134 CERN Tested. 5/26
2135 CERN Tested. HTR13 LED broken. Now fixed. 5/26
2136 CERN Tested. 5/26
2137 CERN Tested. Initially 2 errors. 2nd time tested-no errors. Probably a wiring issue. 5/26
2138 CERN Tested. 5/26
2139 CERN Tested. 5/26
2140 CERN Tested. Initially 2 errors. 2nd time tested-no errors. Probably a wiring issue. 5/26
2141 CERN Tested. 5/26
2142 CERN Tested. 5/26
 
2143 BU Tested. Ethernet error(RJ 45). Was not fixed. Accidentally shipped 5/26
Changed:
<
<
2144 BU Tested. 5/26
2145 BU Tested. 5/26
2146 BU Tested. SLINK and CRC errors.
>
>
2144 CERN Tested. 5/26
2145 CERN Tested. 5/26
2146 BU Tested. SLINK and CRC errors.  
 
2147 BU Tested. Two broken LEDs, Ethernet error(RJ 45), and CRC error.
Changed:
<
<
2148 BU Tested. 5/26
>
>
2148 CERN Tested. 5/26
 
2149 BU Tested. DSP error
Changed:
<
<
2150 BU Tested.
2151 BU Tested.
2152 BU Tested.
2153 BU Tested.
2154 BU Tested.
2155 BU Tested.
2156 BU Tested.
2157 BU Tested.
2158 BU Tested.
2159 BU Tested.
2160 BU Tested.
2161 BU Tested.
2162 BU Tested.
2163 BU Tested.
>
>
2150 BU Tested.  
2151 BU Tested. 6/1
2152 BU Tested. 6/1
2153 BU Tested. 6/1
2154 BU Tested. 6/1
2155 BU Tested. 6/1
2156 BU Tested. 6/1
2157 BU Tested. 6/1
2158 BU Tested. 6/1
2159 BU Tested. 6/1
2160 BU Tested. 6/1
2161 BU Tested. 6/1
2162 BU Tested. 6/1
2163 BU Tested. 6/1
  EricHazen - 15 Apr 2009

Revision 629 May 2009 - AshleyRubinstein

Line: 1 to 1
 
META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not compatible with the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 26 to 26
 The production board serial numbers start with 2129 as shown below. On the PCB, the binary "jumpers" (actually cut traces) star with "10000001".
Changed:
<
<
S/N Location Notes
2129 BU Tested. Shipped 5/26
2130 BU Tested. Shipped 5/26
2131 BU Tested. Shipped 5/26
2132 BU Tested. Shipped 5/26
2133 BU Tested. Shipped 5/26
2134 BU Tested. Shipped 5/26
2135 BU Tested. HTR13 LED broken. Now fixed. Shipped 5/26
2136 BU Tested. Shipped 5/26
2137 BU Tested. Initially 2 errors. 2nd time tested-no errors. Probably a wiring issue. Shipped 5/26
2138 BU Tested. Shipped 5/26
2139 BU Tested. Shipped 5/26
2140 BU Tested. Initially 2 errors. 2nd time tested-no errors. Probably a wiring issue. Shipped 5/26
2141 BU Tested. Shipped 5/26
2142 BU Tested. Shipped 5/26
2143 BU Tested. Ethernet error(RJ 45). Was not fixed and was accidentally shipped 5/26
2144 BU Tested. Shipped 5/26
2145 BU Tested. Shipped 5/26
>
>
S/N Location Notes Date shipped
2129 BU Tested. 5/26
2130 BU Tested. 5/26
2131 BU Tested. 5/26