10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to
the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Tested. Initially 2 errors. 2nd time tested-no errors. Probably a wiring issue.
5/26
OK
2141
FED_723
Tested.
5/26
OK
Changed:
< <
2142
FED_705
Prior incident as different FED (3/24/10): Was removed when we had an issue where no HTRs were sending data. No other symptoms point to DCC failure
6/11/10
OK
> >
2142
904 Hospital
Prior incident as different FED (3/24/10): Was removed when we had an issue where no HTRs were sending data. No other symptoms point to DCC failure. Removed on 10 May 2012 due to LRB DRAM failure: eLog Entry
5/10/12
BAD LRB
2143
FED_718
Tested. Ethernet error(RJ 45). Was not fixed. Returned to BU 6/9/09. Tested/shipped back to CERN 23 Jan 2012: Installed as FED 718 http://cmsonline.cern.ch/cms-elog/750159
23 Jan 2012
OK
2144
FED_722
Tested.
5/26
OK
2145
FED_703
"Stops sending events down SLINK and goes to OFW at 80 kHz" . Tested OK by PDL 4/1/11