10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to
the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
Line: 101 to 101
2178
FED_700
Tested. Installed to replace 2160 - 10/29/09
7/1
OK
2179
FNAL
Tested.
Ship to FNAL 2011-05-12
OK
2180
BU
Tested. TTS link error. SLINK error.
Sick
Changed:
< <
2181
904 Hospital
CRC erros and "miscellaneous errors" during intervention on a different DCC problem: http://cmsonline.cern.ch/cms-elog/637389 Was eventually tested for bad memory and failed memory test. This appears to have developed memory issue during the aforementioned intervention
3 Aug 2011
Sick: bad memory
> >
2181
904 Spares
CRC erros and "miscellaneous errors" during intervention on a different DCC problem: http://cmsonline.cern.ch/cms-elog/637389 Was eventually tested for bad memory and failed memory test. This appears to have developed memory issue during the aforementioned intervention 26 Jan 2012: This board had the affected LRB chip replaced at the CERN e-shop. Today it tested AOK at 904. Back to pile of spares
26 Jan 2012
OK
2182
*CERN
Tested.
7/1
OK
2183
BU
Tested.
Ship to MN 2011-05-12
OK
2184
BU
Tested. CRC error, SLINK error. "event size of 4800 words is unreasonable"