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META TOPICPARENT |
name="DCC2Documentation" |
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to
the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black. |
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2156 |
FED_714 |
Tested. |
6/1 |
OK |
2157 |
*CERN |
Tested. Warped board |
6/1 |
OK/warped |
2158 |
BU |
Problem: DSP FW version 0x301c reports as version 0x0 on this board. Can program manually with DCC2Tool.exe w/o issues. CRC of DSP FW reported by DCC2Tool.exe is correct. |
6/1 (returned) |
Sick |
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< < |
2159 |
FED_713 |
Tested. Removed from FED 713 8/18/11 fail LRB4 test |
6/1 |
LRB4 sick |
|
> > |
2159 |
FED_713 |
Tested. 8/18/11 fail LRB4 test, however, this LRB is not in use (no spigots attached to HTRs) |
6/1 |
LRB4 sick |
|
|
2160 |
904 Hospital |
Removed from FED 700 due to UERR on spigot 13 - 10/29/09. |
6/1 |
Sick |
2161 |
FED_708 |
Tested. |
6/1 |
OK |
2162 |
FED_716 |
Tested. |
6/1 |
OK |
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Changes: |
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< < | S/N 2159 fails LRB4 link/memory test in the pit as FED 713. PDL is swapping it out. |
> > | S/N 2159 fails LRB4 link/memory test in the pit as FED 713. PDL discovered that these spigots are not in use on this FED and opted not to swap out. |
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-- EricHazen - 18 Aug 2011 |