Difference: DCC2BoardDatabase (31 vs. 32)

Revision 3201 Apr 2011 - EricHazen

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META TOPICPARENT name="DCC2Documentation"
10 Prototype boards with red front panels were manufactured in early 2009. These boards are not identical to the production boards because they have a smaller FPGA. The production front panels are marked "DCC2" and are black.
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2142 FED_701 Prior incident as different FED (3/24/10): Was removed when we had an issue where no HTRs were sending data. No other symptoms point to DCC failure 6/11/10 OK
2143 BU Tested. Ethernet error(RJ 45). Was not fixed. Returned to BU 6/9/09. Accidentally shipped 5/26 Sick
2144 FED_722 Tested. 5/26 OK
2145 *904 Hospital Stops sending events down SLINK and goes to OFW at 80 kHz 11/16 Sick
2145 904 Spares "Stops sending events down SLINK and goes to OFW at 80 kHz" . Tested OK by PDL 4/1/11 11/16 OK
2146 BU Tested. Pin9 of HTR14 RJ45 to U14 line open. Could be a PCB problem.   Sick
2147 BU Tested. Two broken LEDs, Ethernet error(RJ 45), and CRC error. R25 cold solder,D25 is also missing. Errors fixed as of 6/3   OK
2148 FED_721 Tested. 5/26 OK
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Phil tested SN 2145 at CERN as follows:

Installed HCAL DAQ version 10.4.6 (unrelated, needed for different test)
Altered FedkitTest_LTClistenToTTS_from_slot20 to take SLINK data from slot 20.
Blasted high rate events at DCC. Due to SLINK readout (with only CRC error checking), 
  effective rate was limited to 34 kHz since this DCC was providing TTS signal.
Readout 10E6 events at this rate with no SLINK errors. Good enough for me.

-- EricHazen - 01 Apr 2011

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