There is a quad clock synthesizer (Si5338B) with the following outputs programmed:
clk0 is programmed as 156.25 for T1 with 10Gbit Ethernet SFPs
clk1 feeding both T1 and T2 is programmed as 125.00, SFPs on T1 with DAQLSC is also fed by this clock (this includes both the 5.0Gb/s and 10.0Gb/s fiber DAQ output modes)
clk2 feeding AMC link is programmed as 250.00 (backplane link from AMC cards on Fabric A)
clk3 feeding DDR memory is programmed as 200.00 for new T1 and 225.00 for old T1