Difference: AMC13FirmwareDevelopment (1 vs. 7)

Revision 720 Jan 2012 - EricHazen

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Please log test activity here: AMC13DebugLog
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Test Firmware

Current AMC13 firmware as of 20 Jan 2012 supports TTC distribution plus demonstration DAQ link transmit/receive capability at 5.0Gb/sec from SFP0 to SFP1.]

Register list and description for this firmware is here: AMC13spec.txt

 

Supporting Documents

Revision 609 Dec 2011 - EricHazen

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Please log test activity here: AMC13DebugLog
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Outline plan for AMC13 firmware (initial version for HCAL):

1.  TTC clock / signal distribution, with receiver logic for MiniCTR2B
     (this is maybe already done from last year?)

2.  DAQ data path (backplane readout)
     a)  output to SDRAM spy buffer for IPMI and/or Ethernet readout
     b)  output to optical fiber link (to Xilinx evaluation board, initially)

3.  Trigger path
     Align TP in AMC13 based on BC0, simple trigger algorithm
     Output via TTC SFP fiber at 160Mb/s using TTC protocol

4.  Control/monitoring
     a)  using interface to MMC (SPI or whatever)
     b)  Ethernet using IPbus
          (documentation here: http://projects.hepforge.org/cactus/index.php)
     I suggest that the same set of registers be accessible by Ethernet and SPI

5.  Flash memory programming over Ethernet
 

Supporting Documents

Revision 502 Dec 2011 - EricHazen

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Please log test activity here: AMC13DebugLog
 Outline plan for AMC13 firmware (initial version for HCAL):


Revision 421 Nov 2011 - EricHazen

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Outline plan for AMC13 firmware (initial version for HCAL):
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Revision 307 Nov 2011 - EricHazen

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Outline plan for AMC13 firmware (initial version for HCAL):
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Supporting Documents

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  • CACTUS repository for IPbus etc
 

Revision 206 Nov 2011 - EricHazen

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Outline plan for AMC13 firmware (initial version for HCAL):
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Supporting Documents

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  -- EricHazen - 06 Nov 2011 \ No newline at end of file

Revision 106 Nov 2011 - EricHazen

Line: 1 to 1
Added:
>
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META TOPICPARENT name="HcalDTC"
Outline plan for AMC13 firmware (initial version for HCAL):

1.  TTC clock / signal distribution, with receiver logic for MiniCTR2B
     (this is maybe already done from last year?)

2.  DAQ data path (backplane readout)
     a)  output to SDRAM spy buffer for IPMI and/or Ethernet readout
     b)  output to optical fiber link (to Xilinx evaluation board, initially)

3.  Trigger path
     Align TP in AMC13 based on BC0, simple trigger algorithm
     Output via TTC SFP fiber at 160Mb/s using TTC protocol

4.  Control/monitoring
     a)  using interface to MMC (SPI or whatever)
     b)  Ethernet using IPbus
          (documentation here: http://projects.hepforge.org/cactus/index.php)
     I suggest that the same set of registers be accessible by Ethernet and SPI

5.  Flash memory programming over Ethernet

Supporting Documents

-- EricHazen - 06 Nov 2011

 
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