| |
| META TOPICPARENT |
name="HcalDTC" |
Each AMC13 as shipped is a 3-board stack (T1, T2, T3). The serial number is set by soldered jumpers on the T2 board (8 bits). On AMC13XG the serial number is printed on the front panel label in decimal. |
| |
|
|
<
< |
| 33 (0x21) |
HW Tested |
2.1 |
T1: 0x8a T2: 0x17 |
BU |
T3 reattached (after Clock Tests) |
|
|
>
> |
| 33 (0x21) |
HW Tested |
2.1 |
T1: 0x102 T2: 0x19 |
BU |
T3 reattached (after Clock Tests) FW issues |
|
|
| |
| 34 (0x22) |
HW Tested |
2.1 |
T1: 0x8d T2: 0x17 |
BU, EDF |
(prev at cornell) Won't power up? (Testing, 8/6/2013) Problem seems to be in T1 board. Swapped parts w/ SN 43 for testing. SN34 T2 w/ the SN43 T1 seems to work. SN34 T1 w/ SN43 T2 exhibiting same problems. (Currently disassembled in EDF 2/10/14) |
|
| 35 (0x23) |
HW Tested |
2.0 |
T1: 0x84 T2: 0x17 |
UW Madison |
FW currently broken (IPbus issue) |
|
| 36 (0x24) |
HW Tested |
2.0 |
T1: 0x86 T2: 0x17 |
Imperial College |
FW currently broken (IPbus issue) |
|
| |
|
|
<
< |
| 37 (0x25) |
Some HW Problems |
|
T1: 0x87 T2: 0x17 |
BU, EDF |
Handle mechanism fixed. FPGA Unconfigure after update to 0x89 firmware |
|
|
>
> |
| 37 (0x25) |
Some HW Problems |
|
T1: 0x87 T2: 0x17 |
BU, EDF |
Handle mechanism fixed. FPGA Unconfigure after update to 0x89 firmware (2/10/2014 - Now has T1: 0x102 T2:0x19 firmware and experiencing memory problem) |
|
|
| |
| 38 (0x26) |
HW Tested |
2.0 |
T1: 0x87 T2: 0x17 |
CERN |
FW works at 2.5 Gb/s backplane link speed |
|
| 39 (0x27) |
HW Tested |
2.1 |
T1: 0x8d T2: 0x17 |
Cornell |
Ship to Cornell 7/30/13, returned to BU capacitor on T2 replace and hand carried back to Cornell by Nic (after testing) |
|
| 40 (0x28) |
HW Tested |
2.1 |
T1: 0x100 T2: 0x19 |
BU |
|
|
|
|
<
< |
| 41 (0x29) |
HW Tested |
2.1 |
T1: 0x8d T2: 0x17 |
BU |
Ship 7/29/13 to Magnus c/o Laza |
|
|
>
> |
| 41 (0x29) |
HW Tested |
2.1 |
T1: 0x8d T2: 0x17 |
CERN |
Ship 7/29/13 to Magnus c/o Laza |
|
|
| |
|
|
<
< |
| 42 (0x2a) |
HW Tested |
2.1 |
T1: 0x100 T2: 0x19 |
BU |
Working (12/13). T1 Error gone after firmware upgrade to 0x94, production test still needed. (11/8) After upgrade to 0x95 and 0x18 by Mr. Wu: passed production test. |
|
|
>
> |
| 42 (0x2a) |
HW Tested |
2.1 |
T1: 0x100 T2: 0x19 |
BU |
|
|
|
| |
| 43 (0x2b) |
HW Tested |
2.1 |
T1: 0x100 T2: 0x19 |
BU |
Working (12/13) T3 reattached (after Clock Tests) , swapped parts w/ SN 39 for testing. SN 43 front panel attached to SN43 T1 and SN39T2. SN43 T2 in bag labelled SN43 |
|
| 44 (0x2c) |
HW Tested |
2.1 |
T1: 0x8d T2:0x17 |
CERN |
Ship 7/29/13 to Magnus c/o Laza , experiencing problems communicating w/ board |
|
| 45 (0x2d) |
HW Tested |
2.1 |
T1:0x94 T2: 0x17 |
CERN |
Ship 10/1/13 to CERN, Laza |
|
|
| | Version 6 (S6) is the first version with the "final" flash layout with golden (backup) configuration.
Modules with a T2 version earlier than S6 can be updated first by programming S6 to flash address 0x0 (may require older software) and then using the current software to program the Header (0x0), Golden (0x100000), Spartan (0x200000), and Virtex (0x400000). One this is done, new firmware may be loaded from the flash by software command without power cycle. |
|
>
> |
|
| | -- EricHazen - 24 Jan 2012, appended J. Rohlf 26 May 2012
\ No newline at end of file |
Copyright © 2008-2023 by the contributing authors. All material on this collaboration platform is the property of the contributing authors.